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authorJim Grosbach <grosbach@apple.com>2012-01-21 00:07:56 +0000
committerJim Grosbach <grosbach@apple.com>2012-01-21 00:07:56 +0000
commit78dcaed8ca82ae64243697d3fa974b4e790f8c50 (patch)
tree264d6f59f6c1c45a865ee714b758d18165140772 /llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
parent384dd631894fc73668a75c03f7c04f7849ef5a6a (diff)
downloadbcm5719-llvm-78dcaed8ca82ae64243697d3fa974b4e790f8c50.tar.gz
bcm5719-llvm-78dcaed8ca82ae64243697d3fa974b4e790f8c50.zip
Thumb2 'add rd, pc, imm' alternate form for 'adr' instruction.
llvm-svn: 148601
Diffstat (limited to 'llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp')
-rw-r--r--llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp4
1 files changed, 3 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index 84814f16bc9..a520bfff6d3 100644
--- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -4628,9 +4628,11 @@ bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
//
// If either register is a high reg, it's either one of the SP
// variants (handled above) or a 32-bit encoding, so we just
- // check against T3.
+ // check against T3. If the second register is the PC, this is an
+ // alternate form of ADR, which uses encoding T4, so check for that too.
if ((!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
!isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg())) &&
+ static_cast<ARMOperand*>(Operands[4])->getReg() != ARM::PC &&
static_cast<ARMOperand*>(Operands[5])->isT2SOImm())
return false;
// If both registers are low, we're in an IT block, and the immediate is
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