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author | Daniel Dunbar <daniel@zuster.org> | 2011-01-18 05:34:05 +0000 |
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committer | Daniel Dunbar <daniel@zuster.org> | 2011-01-18 05:34:05 +0000 |
commit | 5d99420e113d7f45d2420914abbdd5ca5267f37b (patch) | |
tree | 651631c4e0d794e24f8e68f082ea04a4250bf7d4 /llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp | |
parent | d8da9e0fe61fd8db42f1667f96698263a4a61870 (diff) | |
download | bcm5719-llvm-5d99420e113d7f45d2420914abbdd5ca5267f37b.tar.gz bcm5719-llvm-5d99420e113d7f45d2420914abbdd5ca5267f37b.zip |
McARM: Add a variety of asserts on the sanity of memory operands.
llvm-svn: 123737
Diffstat (limited to 'llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp')
-rw-r--r-- | llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp index 7125e98c6e9..5d3b147bf46 100644 --- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -415,11 +415,20 @@ public: } static ARMOperand *CreateMem(unsigned BaseRegNum, bool OffsetIsReg, - const MCExpr *Offset, unsigned OffsetRegNum, + const MCExpr *Offset, int OffsetRegNum, bool OffsetRegShifted, enum ShiftType ShiftType, const MCExpr *ShiftAmount, bool Preindexed, bool Postindexed, bool Negative, bool Writeback, SMLoc S, SMLoc E) { + assert((OffsetRegNum == -1 || OffsetIsReg) && + "OffsetRegNum must imply OffsetIsReg!"); + assert((!OffsetRegShifted || OffsetIsReg) && + "OffsetRegShifted must imply OffsetIsReg!"); + assert((!ShiftAmount || (OffsetIsReg && OffsetRegShifted)) && + "Cannot have shift amount without shifted register offset!"); + assert((!Offset || !OffsetIsReg) && + "Cannot have expression offset and register offset!"); + ARMOperand *Op = new ARMOperand(Memory); Op->Mem.BaseRegNum = BaseRegNum; Op->Mem.OffsetIsReg = OffsetIsReg; |