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authorAnton Korobeynikov <asl@math.spbu.ru>2010-04-07 18:21:46 +0000
committerAnton Korobeynikov <asl@math.spbu.ru>2010-04-07 18:21:46 +0000
commit4fb6a66c8fde94abf9887f1c838f8d1a2c3e802a (patch)
tree1b16bfc307ace024376c9657c72bcc9161c0949d /llvm/lib/Target/ARM/ARMTargetMachine.cpp
parent982f0ceaf8573518a379f2504f1f978432495a44 (diff)
downloadbcm5719-llvm-4fb6a66c8fde94abf9887f1c838f8d1a2c3e802a.tar.gz
bcm5719-llvm-4fb6a66c8fde94abf9887f1c838f8d1a2c3e802a.zip
Move NEON-VFP domain fixer upper, so post-RA scheduler would benefit from it.
llvm-svn: 100668
Diffstat (limited to 'llvm/lib/Target/ARM/ARMTargetMachine.cpp')
-rw-r--r--llvm/lib/Target/ARM/ARMTargetMachine.cpp10
1 files changed, 6 insertions, 4 deletions
diff --git a/llvm/lib/Target/ARM/ARMTargetMachine.cpp b/llvm/lib/Target/ARM/ARMTargetMachine.cpp
index ab299b13b78..f769702cf4e 100644
--- a/llvm/lib/Target/ARM/ARMTargetMachine.cpp
+++ b/llvm/lib/Target/ARM/ARMTargetMachine.cpp
@@ -108,8 +108,12 @@ bool ARMBaseTargetMachine::addPreRegAlloc(PassManagerBase &PM,
bool ARMBaseTargetMachine::addPreSched2(PassManagerBase &PM,
CodeGenOpt::Level OptLevel) {
// FIXME: temporarily disabling load / store optimization pass for Thumb1.
- if (OptLevel != CodeGenOpt::None && !Subtarget.isThumb1Only())
- PM.add(createARMLoadStoreOptimizationPass());
+ if (OptLevel != CodeGenOpt::None) {
+ if (!Subtarget.isThumb1Only())
+ PM.add(createARMLoadStoreOptimizationPass());
+ if (Subtarget.hasNEON())
+ PM.add(createNEONMoveFixPass());
+ }
// Expand some pseudo instructions into multiple instructions to allow
// proper scheduling.
@@ -124,8 +128,6 @@ bool ARMBaseTargetMachine::addPreEmitPass(PassManagerBase &PM,
if (OptLevel != CodeGenOpt::None) {
if (!Subtarget.isThumb1Only())
PM.add(createIfConverterPass());
- if (Subtarget.hasNEON())
- PM.add(createNEONMoveFixPass());
}
if (Subtarget.isThumb2()) {
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