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| author | Vladimir Sukharev <vladimir.sukharev@arm.com> | 2015-03-26 17:05:54 +0000 |
|---|---|---|
| committer | Vladimir Sukharev <vladimir.sukharev@arm.com> | 2015-03-26 17:05:54 +0000 |
| commit | c632cda8b2fc26a047eca25620c52d1f843332f7 (patch) | |
| tree | 2748557e99ed89b960e56e049fe9782a7a0b6f3c /llvm/lib/Target/ARM/ARMSubtarget.h | |
| parent | cdf1e2e36370605abdeb47cf1721897036354370 (diff) | |
| download | bcm5719-llvm-c632cda8b2fc26a047eca25620c52d1f843332f7.tar.gz bcm5719-llvm-c632cda8b2fc26a047eca25620c52d1f843332f7.zip | |
[AArch64, ARM] Add v8.1a architecture and generic cpu
New architecture and cpu added, following http://community.arm.com/groups/processors/blog/2014/12/02/the-armv8-a-architecture-and-its-ongoing-development
Reviewers: t.p.northover
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D8505
llvm-svn: 233290
Diffstat (limited to 'llvm/lib/Target/ARM/ARMSubtarget.h')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMSubtarget.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/ARMSubtarget.h b/llvm/lib/Target/ARM/ARMSubtarget.h index fc1176d85d1..aaa35614f1e 100644 --- a/llvm/lib/Target/ARM/ARMSubtarget.h +++ b/llvm/lib/Target/ARM/ARMSubtarget.h @@ -182,6 +182,9 @@ protected: /// HasCRC - if true, processor supports CRC instructions bool HasCRC; + /// HasV8_1a - if true, the processor has V8.1a: PAN and RDMA extensions + bool HasV8_1a; + /// If true, the instructions "vmov.i32 d0, #0" and "vmov.i32 q0, #0" are /// particularly effective at zeroing a VFP register. bool HasZeroCycleZeroing; @@ -310,6 +313,7 @@ public: bool hasNEON() const { return HasNEON; } bool hasCrypto() const { return HasCrypto; } bool hasCRC() const { return HasCRC; } + bool hasV8_1a() const { return HasV8_1a; } bool hasVirtualization() const { return HasVirtualization; } bool useNEONForSinglePrecisionFP() const { return hasNEON() && UseNEONForSinglePrecisionFP; |
