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| author | Evan Cheng <evan.cheng@apple.com> | 2010-10-07 01:50:48 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2010-10-07 01:50:48 +0000 |
| commit | 1958cefd69df5d2abae090dc38dabf99d9c9d333 (patch) | |
| tree | fc22a84875c40205da6c763ae8864ba9ee5862d1 /llvm/lib/Target/ARM/ARMScheduleA8.td | |
| parent | 67677515ac911ed94bc4ec79eba89c841b861285 (diff) | |
| download | bcm5719-llvm-1958cefd69df5d2abae090dc38dabf99d9c9d333.tar.gz bcm5719-llvm-1958cefd69df5d2abae090dc38dabf99d9c9d333.zip | |
Model operand cycles of vldm / vstm; also fixes scheduling itineraries of vldr / vstr, etc.
llvm-svn: 115898
Diffstat (limited to 'llvm/lib/Target/ARM/ARMScheduleA8.td')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMScheduleA8.td | 36 |
1 files changed, 20 insertions, 16 deletions
diff --git a/llvm/lib/Target/ARM/ARMScheduleA8.td b/llvm/lib/Target/ARM/ARMScheduleA8.td index 714bf2e6353..ac4da75e960 100644 --- a/llvm/lib/Target/ARM/ARMScheduleA8.td +++ b/llvm/lib/Target/ARM/ARMScheduleA8.td @@ -414,54 +414,58 @@ def CortexA8Itineraries : ProcessorItineraries< InstrItinData<IIC_fpLoad32, [InstrStage<1, [A8_Issue], 0>, InstrStage<1, [A8_Pipe0, A8_Pipe1]>, InstrStage<1, [A8_LdSt0], 0>, - InstrStage<1, [A8_NLSPipe]>], + InstrStage<2, [A8_NLSPipe]>], [2, 1]>, // // Double-precision FP Load // use A8_Issue to enforce the 1 load/store per cycle limit InstrItinData<IIC_fpLoad64, [InstrStage<2, [A8_Issue], 0>, - InstrStage<1, [A8_Pipe0], 0>, - InstrStage<1, [A8_Pipe1]>, InstrStage<1, [A8_Pipe0, A8_Pipe1]>, InstrStage<1, [A8_LdSt0], 0>, - InstrStage<1, [A8_NLSPipe]>], + InstrStage<2, [A8_NLSPipe]>], [2, 1]>, // // FP Load Multiple // use A8_Issue to enforce the 1 load/store per cycle limit - InstrItinData<IIC_fpLoadm, [InstrStage<3, [A8_Issue], 0>, - InstrStage<2, [A8_Pipe0], 0>, - InstrStage<2, [A8_Pipe1]>, + InstrItinData<IIC_fpLoad_m, [InstrStage<3, [A8_Issue], 0>, InstrStage<1, [A8_Pipe0, A8_Pipe1]>, InstrStage<1, [A8_LdSt0], 0>, - InstrStage<1, [A8_NLSPipe]>]>, + InstrStage<1, [A8_NLSPipe]>], [1, 1, 1, 2]>, + // + // FP Load Multiple + update + InstrItinData<IIC_fpLoad_mu,[InstrStage<3, [A8_Issue], 0>, + InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrStage<1, [A8_LdSt0], 0>, + InstrStage<1, [A8_NLSPipe]>], [2, 1, 1, 1, 2]>, // // Single-precision FP Store // use A8_Issue to enforce the 1 load/store per cycle limit InstrItinData<IIC_fpStore32,[InstrStage<1, [A8_Issue], 0>, InstrStage<1, [A8_Pipe0, A8_Pipe1]>, InstrStage<1, [A8_LdSt0], 0>, - InstrStage<1, [A8_NLSPipe]>], + InstrStage<2, [A8_NLSPipe]>], [1, 1]>, // // Double-precision FP Store // use A8_Issue to enforce the 1 load/store per cycle limit InstrItinData<IIC_fpStore64,[InstrStage<2, [A8_Issue], 0>, - InstrStage<1, [A8_Pipe0], 0>, - InstrStage<1, [A8_Pipe1]>, InstrStage<1, [A8_Pipe0, A8_Pipe1]>, InstrStage<1, [A8_LdSt0], 0>, - InstrStage<1, [A8_NLSPipe]>], + InstrStage<2, [A8_NLSPipe]>], [1, 1]>, // // FP Store Multiple // use A8_Issue to enforce the 1 load/store per cycle limit - InstrItinData<IIC_fpStorem, [InstrStage<3, [A8_Issue], 0>, - InstrStage<2, [A8_Pipe0], 0>, - InstrStage<2, [A8_Pipe1]>, + InstrItinData<IIC_fpStore_m,[InstrStage<3, [A8_Issue], 0>, InstrStage<1, [A8_Pipe0, A8_Pipe1]>, InstrStage<1, [A8_LdSt0], 0>, - InstrStage<1, [A8_NLSPipe]>]>, + InstrStage<1, [A8_NLSPipe]>], [1, 1, 1, 1]>, + // + // FP Store Multiple + update + InstrItinData<IIC_fpStore_mu,[InstrStage<3, [A8_Issue], 0>, + InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrStage<1, [A8_LdSt0], 0>, + InstrStage<1, [A8_NLSPipe]>], [2, 1, 1, 1, 1]>, // NEON // Issue through integer pipeline, and execute in NEON unit. |
