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authorDavid Goodwin <david_goodwin@apple.com>2009-07-08 18:31:39 +0000
committerDavid Goodwin <david_goodwin@apple.com>2009-07-08 18:31:39 +0000
commit9ca33e8a9fd35a0ef0ea99e3a31ba280e38ec630 (patch)
tree7735246505db947cc990733d112faae477db0c18 /llvm/lib/Target/ARM/ARMRegisterInfo.h
parentf731a2df6bfba51769913bb0afe59c7cb7154130 (diff)
downloadbcm5719-llvm-9ca33e8a9fd35a0ef0ea99e3a31ba280e38ec630.tar.gz
bcm5719-llvm-9ca33e8a9fd35a0ef0ea99e3a31ba280e38ec630.zip
Push methods into base class in preparation for sharing.
llvm-svn: 75020
Diffstat (limited to 'llvm/lib/Target/ARM/ARMRegisterInfo.h')
-rw-r--r--llvm/lib/Target/ARM/ARMRegisterInfo.h30
1 files changed, 2 insertions, 28 deletions
diff --git a/llvm/lib/Target/ARM/ARMRegisterInfo.h b/llvm/lib/Target/ARM/ARMRegisterInfo.h
index 403ab73acfe..8edfb9a2057 100644
--- a/llvm/lib/Target/ARM/ARMRegisterInfo.h
+++ b/llvm/lib/Target/ARM/ARMRegisterInfo.h
@@ -20,38 +20,12 @@
namespace llvm {
class ARMSubtarget;
- class TargetInstrInfo;
+ class ARMBaseInstrInfo;
class Type;
struct ARMRegisterInfo : public ARMBaseRegisterInfo {
public:
- ARMRegisterInfo(const TargetInstrInfo &tii, const ARMSubtarget &STI);
-
- /// emitLoadConstPool - Emits a load from constpool to materialize the
- /// specified immediate.
- void emitLoadConstPool(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator &MBBI,
- const TargetInstrInfo *TII, DebugLoc dl,
- unsigned DestReg, int Val,
- ARMCC::CondCodes Pred = ARMCC::AL,
- unsigned PredReg = 0) const;
-
- /// Code Generation virtual methods...
- bool isReservedReg(const MachineFunction &MF, unsigned Reg) const;
-
- bool requiresRegisterScavenging(const MachineFunction &MF) const;
-
- bool hasReservedCallFrame(MachineFunction &MF) const;
-
- void eliminateCallFramePseudoInstr(MachineFunction &MF,
- MachineBasicBlock &MBB,
- MachineBasicBlock::iterator I) const;
-
- void eliminateFrameIndex(MachineBasicBlock::iterator II,
- int SPAdj, RegScavenger *RS = NULL) const;
-
- void emitPrologue(MachineFunction &MF) const;
- void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
+ ARMRegisterInfo(const ARMBaseInstrInfo &tii, const ARMSubtarget &STI);
};
} // end namespace llvm
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