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authorDiana Picus <diana.picus@linaro.org>2017-07-13 11:09:34 +0000
committerDiana Picus <diana.picus@linaro.org>2017-07-13 11:09:34 +0000
commitc4521756425c46d4aa64f0268502401e2fc83e1f (patch)
tree64ac142a961e7681180b8e3cb8d5015660a274cd /llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp
parent50b2dd336e398a4516a693a4356fa1c942783e9f (diff)
downloadbcm5719-llvm-c4521756425c46d4aa64f0268502401e2fc83e1f.tar.gz
bcm5719-llvm-c4521756425c46d4aa64f0268502401e2fc83e1f.zip
[ARM] GlobalISel: Support G_BR
This boils down to not crashing in reg bank select due to the lack of register operands on this instruction, and adding some tests. The instruction selection is already covered by the TableGen'erated code. llvm-svn: 307904
Diffstat (limited to 'llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp')
-rw-r--r--llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp3
1 files changed, 3 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp b/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp
index 31c622a5717..6e93aafc2ad 100644
--- a/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp
@@ -331,6 +331,9 @@ ARMRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
&ARM::ValueMappings[ARM::DPR3OpsIdx]});
break;
}
+ case G_BR:
+ OperandsMapping = getOperandsMapping({nullptr});
+ break;
default:
return getInvalidInstructionMapping();
}
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