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| author | Diana Picus <diana.picus@linaro.org> | 2017-11-23 13:26:07 +0000 |
|---|---|---|
| committer | Diana Picus <diana.picus@linaro.org> | 2017-11-23 13:26:07 +0000 |
| commit | c01f7f131bd82659fa484cfd6fc9b8a495b2e5ae (patch) | |
| tree | d54fcdaf93a17e6c572f0f0ab51c69e1be3c8d03 /llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp | |
| parent | a0903c6e5d28378373943799b049bb656813c5dc (diff) | |
| download | bcm5719-llvm-c01f7f131bd82659fa484cfd6fc9b8a495b2e5ae.tar.gz bcm5719-llvm-c01f7f131bd82659fa484cfd6fc9b8a495b2e5ae.zip | |
[ARM GlobalISel] Support G_FDIV for s32 and s64
TableGen already generates code for selecting a G_FDIV, so we only need
to add a test.
For the legalizer and reg bank select, we do the same thing as for the
other floating point binary operations: either mark as legal if we have
a FP unit or lower to a libcall, and map to the floating point
registers.
llvm-svn: 318915
Diffstat (limited to 'llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp b/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp index bcae1c93974..b32bfd44954 100644 --- a/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp +++ b/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp @@ -244,7 +244,8 @@ ARMRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { } case G_FADD: case G_FSUB: - case G_FMUL: { + case G_FMUL: + case G_FDIV: { LLT Ty = MRI.getType(MI.getOperand(0).getReg()); OperandsMapping =Ty.getSizeInBits() == 64 ? &ARM::ValueMappings[ARM::DPR3OpsIdx] |
