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| author | Diana Picus <diana.picus@linaro.org> | 2017-05-11 08:28:31 +0000 |
|---|---|---|
| committer | Diana Picus <diana.picus@linaro.org> | 2017-05-11 08:28:31 +0000 |
| commit | 657bfd330204a748d5b5f9bca4fd50199f913240 (patch) | |
| tree | 4a3c7636b33a6e36ebd00da9dd0f12a5a28724a7 /llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp | |
| parent | 738d3b97af3aa7fd8878879a639ba48a6254dbe8 (diff) | |
| download | bcm5719-llvm-657bfd330204a748d5b5f9bca4fd50199f913240.tar.gz bcm5719-llvm-657bfd330204a748d5b5f9bca4fd50199f913240.zip | |
[ARM][GlobalISel] Support for G_ANYEXT
G_ANYEXT can be introduced by the legalizer when widening scalars. Add
support for it in the register bank info (same mapping as everything
else) and in the instruction selector.
When selecting it, we treat it as a COPY, just like G_TRUNC. On this
occasion we get rid of some assertions in selectCopy so we can reuse it.
This shouldn't be a problem at the moment since we're not supporting any
complicated cases (e.g. FPR, different register banks). We might want to
separate the paths when we do.
llvm-svn: 302778
Diffstat (limited to 'llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp b/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp index 13a32211f88..a20997c95cd 100644 --- a/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp +++ b/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp @@ -225,6 +225,7 @@ ARMRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { case G_UDIV: case G_SEXT: case G_ZEXT: + case G_ANYEXT: case G_TRUNC: case G_GEP: // FIXME: We're abusing the fact that everything lives in a GPR for now; in |
