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authorDiana Picus <diana.picus@linaro.org>2017-06-19 09:40:51 +0000
committerDiana Picus <diana.picus@linaro.org>2017-06-19 09:40:51 +0000
commit621894ac76c2ebfaf9c6a601c21550bdf3dc50d6 (patch)
treec4b688c248ac26913f459ce6b18bb959a1e27a59 /llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp
parentf4a09e55a6865ce812d2a24c500d88c340fd4897 (diff)
downloadbcm5719-llvm-621894ac76c2ebfaf9c6a601c21550bdf3dc50d6.tar.gz
bcm5719-llvm-621894ac76c2ebfaf9c6a601c21550bdf3dc50d6.zip
[ARM] GlobalISel: Support G_ICMP for i32 and pointers
Add support throughout the pipeline: - mark as legal for s32 and pointers - map to GPRs - lower to a sequence of instructions, which moves 0 or 1 into the result register based on the flags set by a CMPrr We have copied from FastISel a helper function which maps CmpInst predicates into ARMCC codes. Ideally, we should be able to move it somewhere that both FastISel and GlobalISel can use. llvm-svn: 305672
Diffstat (limited to 'llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp')
-rw-r--r--llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp10
1 files changed, 10 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp b/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp
index f59b075e6dd..2350d0c6ef6 100644
--- a/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp
@@ -255,6 +255,16 @@ ARMRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
OperandsMapping =
getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx], nullptr});
break;
+ case G_ICMP: {
+ LLT Ty2 = MRI.getType(MI.getOperand(2).getReg());
+ (void)Ty2;
+ assert(Ty2.getSizeInBits() == 32 && "Unsupported size for G_ICMP");
+ OperandsMapping =
+ getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx], nullptr,
+ &ARM::ValueMappings[ARM::GPR3OpsIdx],
+ &ARM::ValueMappings[ARM::GPR3OpsIdx]});
+ break;
+ }
case G_MERGE_VALUES: {
// We only support G_MERGE_VALUES for creating a double precision floating
// point value out of two GPRs.
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