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author | Diana Picus <diana.picus@linaro.org> | 2017-02-08 13:23:04 +0000 |
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committer | Diana Picus <diana.picus@linaro.org> | 2017-02-08 13:23:04 +0000 |
commit | 4fa83c03fd7b33bf826bfc05d370df038329e826 (patch) | |
tree | 65a90fd4f781b245a0bea87f2629bb0c27fb68c4 /llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp | |
parent | e22fbcb2640354f042fb355bfc426d515cf8a67a (diff) | |
download | bcm5719-llvm-4fa83c03fd7b33bf826bfc05d370df038329e826.tar.gz bcm5719-llvm-4fa83c03fd7b33bf826bfc05d370df038329e826.zip |
[ARM] GlobalISel: Add FPR reg bank
Add a register bank for floating point values and select simple instructions
using them (add, copies from GPR).
This assumes that the hardware can cope with a single precision add (VADDS)
instruction, so the legalizer will treat G_FADD as legal and the instruction
selector will refuse to select if the hardware doesn't support it. In the future
we'll want to be more careful about this, and legalize to libcalls if we have to
use soft float.
llvm-svn: 294442
Diffstat (limited to 'llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp')
-rw-r--r-- | llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp b/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp index f65b6787697..dc111069921 100644 --- a/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp +++ b/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp @@ -33,9 +33,11 @@ using namespace llvm; namespace llvm { namespace ARM { RegisterBankInfo::PartialMapping GPRPartialMapping{0, 32, GPRRegBank}; +RegisterBankInfo::PartialMapping FPRPartialMapping{0, 32, FPRRegBank}; RegisterBankInfo::ValueMapping ValueMappings[] = { - {&GPRPartialMapping, 1}, {&GPRPartialMapping, 1}, {&GPRPartialMapping, 1}}; + {&GPRPartialMapping, 1}, {&GPRPartialMapping, 1}, {&GPRPartialMapping, 1}, + {&FPRPartialMapping, 1}, {&FPRPartialMapping, 1}, {&FPRPartialMapping, 1}}; } // end namespace arm } // end namespace llvm @@ -82,6 +84,9 @@ const RegisterBank &ARMRegisterBankInfo::getRegBankFromRegClass( case GPRnopcRegClassID: case tGPR_and_tcGPRRegClassID: return getRegBank(ARM::GPRRegBankID); + case SPR_8RegClassID: + case SPRRegClassID: + return getRegBank(ARM::FPRRegBankID); default: llvm_unreachable("Unsupported register kind"); } @@ -115,6 +120,9 @@ ARMRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { // the real world we would use different mappings. OperandsMapping = &ARM::ValueMappings[0]; break; + case G_FADD: + OperandsMapping = &ARM::ValueMappings[3]; + break; case G_FRAME_INDEX: OperandsMapping = getOperandsMapping({&ARM::ValueMappings[0], nullptr}); break; |