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| author | Diana Picus <diana.picus@linaro.org> | 2017-06-07 11:57:30 +0000 |
|---|---|---|
| committer | Diana Picus <diana.picus@linaro.org> | 2017-06-07 11:57:30 +0000 |
| commit | 0196427b037d4830ff38c4bc3c75429998b6a0a0 (patch) | |
| tree | 4b251f738488cddd6b538d935d3389e2dec5de2f /llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp | |
| parent | cc524bf6ac21bb3943b3c802306e0bfb718eade2 (diff) | |
| download | bcm5719-llvm-0196427b037d4830ff38c4bc3c75429998b6a0a0.tar.gz bcm5719-llvm-0196427b037d4830ff38c4bc3c75429998b6a0a0.zip | |
[ARM] GlobalISel: Support G_XOR
Same as the other binary operators:
- legalize to 32 bits
- map to GPRs
- select to EORrr via TableGen'erated code
llvm-svn: 304898
Diffstat (limited to 'llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp b/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp index b4df168fc32..898f1bcc4cc 100644 --- a/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp +++ b/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp @@ -223,6 +223,7 @@ ARMRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { case G_MUL: case G_AND: case G_OR: + case G_XOR: case G_SDIV: case G_UDIV: case G_SEXT: |
