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author | Tim Northover <tnorthover@apple.com> | 2014-11-05 00:27:13 +0000 |
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committer | Tim Northover <tnorthover@apple.com> | 2014-11-05 00:27:13 +0000 |
commit | 228c943f316eea630dfb94e270af7e342bd5dd56 (patch) | |
tree | b8616cc8616979c8b30d4511a3b505699cbf28e0 /llvm/lib/Target/ARM/ARMMachineFunctionInfo.h | |
parent | 445b0657a50fbeefcdcd954f4779c8ae933e8d75 (diff) | |
download | bcm5719-llvm-228c943f316eea630dfb94e270af7e342bd5dd56.tar.gz bcm5719-llvm-228c943f316eea630dfb94e270af7e342bd5dd56.zip |
ARM/Dwarf: correctly align stack before callee-saved VPRs
We were making an attempt to do this by adding an extra callee-saved GPR (so
that there was an even number in the list), but when that failed we went ahead
and pushed anyway.
This had a couple of potential issues:
+ The .cfi directives we emit misplaced dN because they were based on
PrologEpilogInserter's calculation.
+ Unaligned stores can be less efficient.
+ Unaligned stores can actually fault (likely only an issue in niche cases,
but possible).
This adds a final explicit stack adjustment if all other options fail, so that
the actual locations of the registers match up with where they should be.
llvm-svn: 221320
Diffstat (limited to 'llvm/lib/Target/ARM/ARMMachineFunctionInfo.h')
-rw-r--r-- | llvm/lib/Target/ARM/ARMMachineFunctionInfo.h | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/ARMMachineFunctionInfo.h b/llvm/lib/Target/ARM/ARMMachineFunctionInfo.h index 4f9ea7abb0d..4e67fa13638 100644 --- a/llvm/lib/Target/ARM/ARMMachineFunctionInfo.h +++ b/llvm/lib/Target/ARM/ARMMachineFunctionInfo.h @@ -86,6 +86,7 @@ class ARMFunctionInfo : public MachineFunctionInfo { /// areas. unsigned GPRCS1Size; unsigned GPRCS2Size; + unsigned DPRCSAlignGapSize; unsigned DPRCSSize; /// NumAlignedDPRCS2Regs - The number of callee-saved DPRs that are saved in @@ -134,7 +135,7 @@ public: RestoreSPFromFP(false), LRSpilledForFarJump(false), FramePtrSpillOffset(0), GPRCS1Offset(0), GPRCS2Offset(0), DPRCSOffset(0), - GPRCS1Size(0), GPRCS2Size(0), DPRCSSize(0), + GPRCS1Size(0), GPRCS2Size(0), DPRCSAlignGapSize(0), DPRCSSize(0), NumAlignedDPRCS2Regs(0), JumpTableUId(0), PICLabelUId(0), VarArgsFrameIndex(0), HasITBlocks(false), GlobalBaseReg(0) {} @@ -183,10 +184,12 @@ public: unsigned getGPRCalleeSavedArea1Size() const { return GPRCS1Size; } unsigned getGPRCalleeSavedArea2Size() const { return GPRCS2Size; } + unsigned getDPRCalleeSavedGapSize() const { return DPRCSAlignGapSize; } unsigned getDPRCalleeSavedAreaSize() const { return DPRCSSize; } void setGPRCalleeSavedArea1Size(unsigned s) { GPRCS1Size = s; } void setGPRCalleeSavedArea2Size(unsigned s) { GPRCS2Size = s; } + void setDPRCalleeSavedGapSize(unsigned s) { DPRCSAlignGapSize = s; } void setDPRCalleeSavedAreaSize(unsigned s) { DPRCSSize = s; } unsigned getArgumentStackSize() const { return ArgumentStackSize; } |