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| author | Bob Wilson <bob.wilson@apple.com> | 2010-09-29 17:54:10 +0000 |
|---|---|---|
| committer | Bob Wilson <bob.wilson@apple.com> | 2010-09-29 17:54:10 +0000 |
| commit | 97bf273870265c3977b6485d37a93f026b567daf (patch) | |
| tree | a89ccd9d69411acad3443a4fc6e059c6c9c99a19 /llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp | |
| parent | 620f9d1548a56350e7ad31e1eae85439ecb28382 (diff) | |
| download | bcm5719-llvm-97bf273870265c3977b6485d37a93f026b567daf.tar.gz bcm5719-llvm-97bf273870265c3977b6485d37a93f026b567daf.zip | |
Increase ARM APCS preferred alignment for i64 and f64 from 32 bits to 64 bits.
LDM/STM instructions can run one cycle faster on some ARM processors if the
memory address is 64-bit aligned. Radar 8489376.
llvm-svn: 115047
Diffstat (limited to 'llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp b/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp index ec2b74ac0f3..a7d1d9f3fbd 100644 --- a/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp +++ b/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp @@ -1370,7 +1370,7 @@ ARMPreAllocLoadStoreOpt::CanFormLdStDWord(MachineInstr *Op0, MachineInstr *Op1, unsigned Align = (*Op0->memoperands_begin())->getAlignment(); const Function *Func = MF->getFunction(); unsigned ReqAlign = STI->hasV6Ops() - ? TD->getPrefTypeAlignment(Type::getInt64Ty(Func->getContext())) + ? TD->getABITypeAlignment(Type::getInt64Ty(Func->getContext())) : 8; // Pre-v6 need 8-byte align if (Align < ReqAlign) return false; |
