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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-06-24 16:16:12 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-06-24 16:16:12 +0000 |
| commit | faeaedf8e938696497021adcd5925e5741c72f62 (patch) | |
| tree | 66d3c65d42cfac2b080183c6c79562d0c205b23f /llvm/lib/Target/ARM/ARMLegalizerInfo.cpp | |
| parent | 906d494b6e7eb0d8bde19bec2de7d93a9516ebe3 (diff) | |
| download | bcm5719-llvm-faeaedf8e938696497021adcd5925e5741c72f62.tar.gz bcm5719-llvm-faeaedf8e938696497021adcd5925e5741c72f62.zip | |
GlobalISel: Remove unsigned variant of SrcOp
Force using Register.
One downside is the generated register enums require explicit
conversion.
llvm-svn: 364194
Diffstat (limited to 'llvm/lib/Target/ARM/ARMLegalizerInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMLegalizerInfo.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp b/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp index 701c7366234..796eaeedee7 100644 --- a/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp +++ b/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp @@ -423,7 +423,7 @@ bool ARMLegalizerInfo::legalizeCustom(MachineInstr &MI, auto *ArgTy = OpSize == 32 ? Type::getFloatTy(Ctx) : Type::getDoubleTy(Ctx); auto *RetTy = Type::getInt32Ty(Ctx); - SmallVector<unsigned, 2> Results; + SmallVector<Register, 2> Results; for (auto Libcall : Libcalls) { auto LibcallResult = MRI.createGenericVirtualRegister(LLT::scalar(32)); auto Status = |
