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author | Diana Picus <diana.picus@linaro.org> | 2017-06-07 10:14:23 +0000 |
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committer | Diana Picus <diana.picus@linaro.org> | 2017-06-07 10:14:23 +0000 |
commit | eeb0aad8e4041fcc7baed47f0ca2777fcfddbc34 (patch) | |
tree | 68f55c74ae761c53f8925d903bb56d85c60ed46c /llvm/lib/Target/ARM/ARMLegalizerInfo.cpp | |
parent | 15b80a5b2354d7d32f8c1c3f4fe47cee83d56d79 (diff) | |
download | bcm5719-llvm-eeb0aad8e4041fcc7baed47f0ca2777fcfddbc34.tar.gz bcm5719-llvm-eeb0aad8e4041fcc7baed47f0ca2777fcfddbc34.zip |
[ARM] GlobalISel: Support G_OR
Same as the other binary operators:
- legalize to 32 bits
- map to GPRs
- select ORRrr thanks to TableGen'erated code
llvm-svn: 304890
Diffstat (limited to 'llvm/lib/Target/ARM/ARMLegalizerInfo.cpp')
-rw-r--r-- | llvm/lib/Target/ARM/ARMLegalizerInfo.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp b/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp index b645b83844c..86826a93e14 100644 --- a/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp +++ b/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp @@ -45,7 +45,7 @@ ARMLegalizerInfo::ARMLegalizerInfo(const ARMSubtarget &ST) { setAction({Op, 1, p0}, Legal); } - for (unsigned Op : {G_ADD, G_SUB, G_MUL, G_AND}) { + for (unsigned Op : {G_ADD, G_SUB, G_MUL, G_AND, G_OR}) { for (auto Ty : {s1, s8, s16}) setAction({Op, Ty}, WidenScalar); setAction({Op, s32}, Legal); |