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| author | Diana Picus <diana.picus@linaro.org> | 2017-04-24 08:20:05 +0000 |
|---|---|---|
| committer | Diana Picus <diana.picus@linaro.org> | 2017-04-24 08:20:05 +0000 |
| commit | b70e88bdec9791538624399131071e56e124641a (patch) | |
| tree | d5f25c705e691f3c17dff80cbc6aad04a0f5c495 /llvm/lib/Target/ARM/ARMLegalizerInfo.cpp | |
| parent | e97822e1b7af54c20f0185340e87168ab4e00dec (diff) | |
| download | bcm5719-llvm-b70e88bdec9791538624399131071e56e124641a.tar.gz bcm5719-llvm-b70e88bdec9791538624399131071e56e124641a.zip | |
[ARM] GlobalISel: Support G_(S|U)DIV for s32
Add support for both targets with hardware division and without. For
hardware division we have to add support throughout the pipeline
(legalizer, reg bank select, instruction select). For targets without
hardware division, we only need to mark it as a libcall.
llvm-svn: 301164
Diffstat (limited to 'llvm/lib/Target/ARM/ARMLegalizerInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMLegalizerInfo.cpp | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp b/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp index fe9681439e6..d1c5d964d95 100644 --- a/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp +++ b/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp @@ -47,6 +47,13 @@ ARMLegalizerInfo::ARMLegalizerInfo(const ARMSubtarget &ST) { for (auto Ty : {s1, s8, s16, s32}) setAction({Op, Ty}, Legal); + for (unsigned Op : {G_SDIV, G_UDIV}) { + if (ST.hasDivideInARMMode()) + setAction({Op, s32}, Legal); + else + setAction({Op, s32}, Libcall); + } + for (unsigned Op : {G_SEXT, G_ZEXT}) { setAction({Op, s32}, Legal); for (auto Ty : {s1, s8, s16}) |
