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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-01-22 21:42:11 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-01-22 21:42:11 +0000 |
| commit | 30989e492b8e32ec5f558777b8988ccea8ce5155 (patch) | |
| tree | 0a0c155f6401d6d57550c97def91988c3598952e /llvm/lib/Target/ARM/ARMLegalizerInfo.cpp | |
| parent | 352695c336112585b10e92d280652c0084ba9650 (diff) | |
| download | bcm5719-llvm-30989e492b8e32ec5f558777b8988ccea8ce5155.tar.gz bcm5719-llvm-30989e492b8e32ec5f558777b8988ccea8ce5155.zip | |
GlobalISel: Allow shift amount to be a different type
For AMDGPU the shift amount is never 64-bit, and
this needs to use a 32-bit shift.
X86 uses i8, but seemed to be hacking around this before.
llvm-svn: 351882
Diffstat (limited to 'llvm/lib/Target/ARM/ARMLegalizerInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMLegalizerInfo.cpp | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp b/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp index e1f7af1a6d8..37a5f3d1e02 100644 --- a/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp +++ b/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp @@ -135,7 +135,12 @@ ARMLegalizerInfo::ARMLegalizerInfo(const ARMSubtarget &ST) { setAction({Op, s32}, Libcall); } - getActionDefinitionsBuilder({G_ASHR, G_LSHR, G_SHL}).legalFor({s32}); + getActionDefinitionsBuilder(G_INTTOPTR).legalFor({{p0, s32}}); + getActionDefinitionsBuilder(G_PTRTOINT).legalFor({{s32, p0}}); + + getActionDefinitionsBuilder({G_ASHR, G_LSHR, G_SHL}) + .legalFor({{s32, s32}}) + .clampScalar(1, s32, s32); if (ST.hasV5TOps()) { getActionDefinitionsBuilder(G_CTLZ) |
