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authorBenjamin Kramer <benny.kra@googlemail.com>2016-12-16 13:13:03 +0000
committerBenjamin Kramer <benny.kra@googlemail.com>2016-12-16 13:13:03 +0000
commit24bf8689dd9e0d5b729ba866cd9833a1a24699c2 (patch)
tree6a8d6adbd50008e11ecdd32d3922fdf85cefbf4a /llvm/lib/Target/ARM/ARMInstructionSelector.cpp
parent812caee65a1c13ebaf4bc419ab1277523339bd27 (diff)
downloadbcm5719-llvm-24bf8689dd9e0d5b729ba866cd9833a1a24699c2.tar.gz
bcm5719-llvm-24bf8689dd9e0d5b729ba866cd9833a1a24699c2.zip
[GlobalISel] Silence unused variable warnings in Release builds.
llvm-svn: 289941
Diffstat (limited to 'llvm/lib/Target/ARM/ARMInstructionSelector.cpp')
-rw-r--r--llvm/lib/Target/ARM/ARMInstructionSelector.cpp9
1 files changed, 4 insertions, 5 deletions
diff --git a/llvm/lib/Target/ARM/ARMInstructionSelector.cpp b/llvm/lib/Target/ARM/ARMInstructionSelector.cpp
index 5d74d76b707..53298f6476d 100644
--- a/llvm/lib/Target/ARM/ARMInstructionSelector.cpp
+++ b/llvm/lib/Target/ARM/ARMInstructionSelector.cpp
@@ -39,13 +39,12 @@ static bool selectCopy(MachineInstr &I, const TargetInstrInfo &TII,
return true;
const RegisterBank *RegBank = RBI.getRegBank(DstReg, MRI, TRI);
+ (void)RegBank;
assert(RegBank && "Can't get reg bank for virtual register");
- const unsigned DstSize = MRI.getType(DstReg).getSizeInBits();
- unsigned SrcReg = I.getOperand(1).getReg();
- const unsigned SrcSize = RBI.getSizeInBits(SrcReg, MRI, TRI);
- (void)SrcSize;
- assert(DstSize == SrcSize && "Copy with different width?!");
+ assert(MRI.getType(DstReg).getSizeInBits() ==
+ RBI.getSizeInBits(I.getOperand(1).getReg(), MRI, TRI) &&
+ "Copy with different width?!");
assert(RegBank->getID() == ARM::GPRRegBankID && "Unsupported reg bank");
const TargetRegisterClass *RC = &ARM::GPRRegClass;
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