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authorJim Grosbach <grosbach@apple.com>2011-07-25 20:49:51 +0000
committerJim Grosbach <grosbach@apple.com>2011-07-25 20:49:51 +0000
commitac798e15331cef5990a2aedcdb4be1ffaf395f5a (patch)
tree733c0548ca8745f94900ae611687eace600d34ce /llvm/lib/Target/ARM/ARMInstrInfo.td
parenteeaab221661e01c506603f773847245b3ed836dc (diff)
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ARM asm operand renaming. Make things a bit more explicit.
llvm-svn: 135959
Diffstat (limited to 'llvm/lib/Target/ARM/ARMInstrInfo.td')
-rw-r--r--llvm/lib/Target/ARM/ARMInstrInfo.td4
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.td b/llvm/lib/Target/ARM/ARMInstrInfo.td
index d927e85a0d5..9edfcd76f8c 100644
--- a/llvm/lib/Target/ARM/ARMInstrInfo.td
+++ b/llvm/lib/Target/ARM/ARMInstrInfo.td
@@ -404,7 +404,7 @@ def shift_imm : Operand<i32> {
}
// shifter_operand operands: so_reg_reg, so_reg_imm, and so_imm.
-def ShiftedRegAsmOperand : AsmOperandClass { let Name = "ShiftedReg"; }
+def ShiftedRegAsmOperand : AsmOperandClass { let Name = "RegShiftedReg"; }
def so_reg_reg : Operand<i32>, // reg reg imm
ComplexPattern<i32, 3, "SelectRegShifterOperand",
[shl, srl, sra, rotr]> {
@@ -414,7 +414,7 @@ def so_reg_reg : Operand<i32>, // reg reg imm
let MIOperandInfo = (ops GPR, GPR, shift_imm);
}
-def ShiftedImmAsmOperand : AsmOperandClass { let Name = "ShiftedImm"; }
+def ShiftedImmAsmOperand : AsmOperandClass { let Name = "RegShiftedImm"; }
def so_reg_imm : Operand<i32>, // reg imm
ComplexPattern<i32, 2, "SelectImmShifterOperand",
[shl, srl, sra, rotr]> {
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