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authorBob Wilson <bob.wilson@apple.com>2009-10-08 18:52:56 +0000
committerBob Wilson <bob.wilson@apple.com>2009-10-08 18:52:56 +0000
commitfac9476589f1350513638ad1c5509573ea6908d4 (patch)
treeb3fd607c2c39a2894fb0e84d63e51bfcbb3472e7 /llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
parent4facd965bd4c86db2ed5dd749ccccd5645d38329 (diff)
downloadbcm5719-llvm-fac9476589f1350513638ad1c5509573ea6908d4.tar.gz
bcm5719-llvm-fac9476589f1350513638ad1c5509573ea6908d4.zip
Clean up some unnecessary initializations.
llvm-svn: 83566
Diffstat (limited to 'llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp')
-rw-r--r--llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp4
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
index da4f037f267..0739d4731df 100644
--- a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -1405,7 +1405,7 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
}
// Quad registers are loaded with two separate instructions, where one
// loads the even registers and the other loads the odd registers.
- EVT RegVT = VT;
+ EVT RegVT;
unsigned Opc2 = 0;
switch (VT.getSimpleVT().SimpleTy) {
default: llvm_unreachable("unhandled vld3 type");
@@ -1465,7 +1465,7 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
}
// Quad registers are loaded with two separate instructions, where one
// loads the even registers and the other loads the odd registers.
- EVT RegVT = VT;
+ EVT RegVT;
unsigned Opc2 = 0;
switch (VT.getSimpleVT().SimpleTy) {
default: llvm_unreachable("unhandled vld4 type");
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