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| author | Francis Visoiu Mistrih <francisvm@yahoo.com> | 2017-11-28 17:15:09 +0000 |
|---|---|---|
| committer | Francis Visoiu Mistrih <francisvm@yahoo.com> | 2017-11-28 17:15:09 +0000 |
| commit | 9d7bb0cb408e993181fc1b28986c7eb3495f28b9 (patch) | |
| tree | 117b65c086189d16940bde7b400f0fd4312d98de /llvm/lib/Target/ARM/ARMFrameLowering.cpp | |
| parent | 2803bfaf001241a98608c263a824a5f5ec542511 (diff) | |
| download | bcm5719-llvm-9d7bb0cb408e993181fc1b28986c7eb3495f28b9.tar.gz bcm5719-llvm-9d7bb0cb408e993181fc1b28986c7eb3495f28b9.zip | |
[CodeGen] Print register names in lowercase in both MIR and debug output
As part of the unification of the debug format and the MIR format,
always print registers as lowercase.
* Only debug printing is affected. It now follows MIR.
Differential Revision: https://reviews.llvm.org/D40417
llvm-svn: 319187
Diffstat (limited to 'llvm/lib/Target/ARM/ARMFrameLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMFrameLowering.cpp | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/llvm/lib/Target/ARM/ARMFrameLowering.cpp b/llvm/lib/Target/ARM/ARMFrameLowering.cpp index d60734ab144..e9a13b9802b 100644 --- a/llvm/lib/Target/ARM/ARMFrameLowering.cpp +++ b/llvm/lib/Target/ARM/ARMFrameLowering.cpp @@ -1832,12 +1832,12 @@ void ARMFrameLowering::determineCalleeSaves(MachineFunction &MF, if (!HasFP) { if (SavedRegs.test(ARM::R7)) { --RegDeficit; - DEBUG(dbgs() << "%R7 is saved low register, RegDeficit = " + DEBUG(dbgs() << "%r7 is saved low register, RegDeficit = " << RegDeficit << "\n"); } else { AvailableRegs.push_back(ARM::R7); DEBUG(dbgs() - << "%R7 is non-saved low register, adding to AvailableRegs\n"); + << "%r7 is non-saved low register, adding to AvailableRegs\n"); } } @@ -1859,11 +1859,11 @@ void ARMFrameLowering::determineCalleeSaves(MachineFunction &MF, MF.getFrameInfo().isReturnAddressTaken())) { if (SavedRegs.test(ARM::LR)) { --RegDeficit; - DEBUG(dbgs() << "%LR is saved register, RegDeficit = " << RegDeficit + DEBUG(dbgs() << "%lr is saved register, RegDeficit = " << RegDeficit << "\n"); } else { AvailableRegs.push_back(ARM::LR); - DEBUG(dbgs() << "%LR is not saved, adding to AvailableRegs\n"); + DEBUG(dbgs() << "%lr is not saved, adding to AvailableRegs\n"); } } |

