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authorSaleem Abdulrasool <compnerd@compnerd.org>2014-05-01 04:19:59 +0000
committerSaleem Abdulrasool <compnerd@compnerd.org>2014-05-01 04:19:59 +0000
commit7158303ad78077a2baa80210cab95d5a015ecd92 (patch)
treecb644cec749f0d02f497d7bfa805eeee2b0103ea /llvm/lib/Target/ARM/ARMFrameLowering.cpp
parentd6c0ba3787331980a725b5c856e52230c0605a86 (diff)
downloadbcm5719-llvm-7158303ad78077a2baa80210cab95d5a015ecd92.tar.gz
bcm5719-llvm-7158303ad78077a2baa80210cab95d5a015ecd92.zip
ARM: fix memory leak, simplify WoA stack probing
This fixes the memory leak introduced with the initial addition of support for WoA stack probing. Now that the pseudo-instruction expansion can handle an external symbol, use that to generate the load which simplifies the logic as well as avoids the memory leak. llvm-svn: 207737
Diffstat (limited to 'llvm/lib/Target/ARM/ARMFrameLowering.cpp')
-rw-r--r--llvm/lib/Target/ARM/ARMFrameLowering.cpp12
1 files changed, 3 insertions, 9 deletions
diff --git a/llvm/lib/Target/ARM/ARMFrameLowering.cpp b/llvm/lib/Target/ARM/ARMFrameLowering.cpp
index af4c97db684..c9000156960 100644
--- a/llvm/lib/Target/ARM/ARMFrameLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMFrameLowering.cpp
@@ -25,7 +25,6 @@
#include "llvm/CodeGen/RegisterScavenging.h"
#include "llvm/IR/CallingConv.h"
#include "llvm/IR/Function.h"
-#include "llvm/IR/Module.h"
#include "llvm/MC/MCContext.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Target/TargetOptions.h"
@@ -316,20 +315,15 @@ void ARMFrameLowering::emitPrologue(MachineFunction &MF) const {
.addReg(ARM::R4, RegState::Implicit);
break;
case CodeModel::Large:
- case CodeModel::JITDefault: {
- LLVMContext &Ctx = MF.getMMI().getModule()->getContext();
- const GlobalValue *F =
- Function::Create(FunctionType::get(Type::getVoidTy(Ctx), false),
- GlobalValue::AvailableExternallyLinkage, "__chkstk");
-
+ case CodeModel::JITDefault:
BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm), ARM::R12)
- .addGlobalAddress(F);
+ .addExternalSymbol("__chkstk");
+
BuildMI(MBB, MBBI, dl, TII.get(ARM::BLX))
.addReg(ARM::R12, RegState::Kill)
.addReg(ARM::R4, RegState::Implicit);
break;
}
- }
AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::t2SUBrr),
ARM::SP)
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