summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/ARM/ARMFastISel.cpp
diff options
context:
space:
mode:
authorEric Christopher <echristo@apple.com>2010-09-29 22:24:45 +0000
committerEric Christopher <echristo@apple.com>2010-09-29 22:24:45 +0000
commitb024be3162edbf7deb18d7a991fd8a0f2eea0506 (patch)
tree40f683e7675e7e2bf0918e9a5e9aa5d6500501a9 /llvm/lib/Target/ARM/ARMFastISel.cpp
parenteb1db1c5477ad7e940551b2c3abd45497ac8be7a (diff)
downloadbcm5719-llvm-b024be3162edbf7deb18d7a991fd8a0f2eea0506.tar.gz
bcm5719-llvm-b024be3162edbf7deb18d7a991fd8a0f2eea0506.zip
Add a convenience variable so I'm not chasing all over looking for
a context. llvm-svn: 115094
Diffstat (limited to 'llvm/lib/Target/ARM/ARMFastISel.cpp')
-rw-r--r--llvm/lib/Target/ARM/ARMFastISel.cpp12
1 files changed, 6 insertions, 6 deletions
diff --git a/llvm/lib/Target/ARM/ARMFastISel.cpp b/llvm/lib/Target/ARM/ARMFastISel.cpp
index 53ae75200f8..a79f2994856 100644
--- a/llvm/lib/Target/ARM/ARMFastISel.cpp
+++ b/llvm/lib/Target/ARM/ARMFastISel.cpp
@@ -61,8 +61,9 @@ class ARMFastISel : public FastISel {
const TargetLowering &TLI;
const ARMFunctionInfo *AFI;
- // Convenience variable to avoid checking all the time.
+ // Convenience variables to avoid some queries.
bool isThumb;
+ LLVMContext *Context;
public:
explicit ARMFastISel(FunctionLoweringInfo &funcInfo)
@@ -73,6 +74,7 @@ class ARMFastISel : public FastISel {
Subtarget = &TM.getSubtarget<ARMSubtarget>();
AFI = funcInfo.MF->getInfo<ARMFunctionInfo>();
isThumb = AFI->isThumbFunction();
+ Context = &funcInfo.Fn->getContext();
}
// Code from FastISel.cpp.
@@ -852,7 +854,7 @@ bool ARMFastISel::SelectCmp(const Instruction *I) {
unsigned MovCCOpc = isThumb ? ARM::tMOVCCi : ARM::MOVCCi;
unsigned DestReg = createResultReg(ARM::GPRRegisterClass);
Constant *Zero
- = ConstantInt::get(Type::getInt32Ty(I->getType()->getContext()), 0);
+ = ConstantInt::get(Type::getInt32Ty(*Context), 0);
unsigned ZeroReg = TargetMaterializeConstant(Zero);
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(MovCCOpc), DestReg)
.addReg(ZeroReg).addImm(1)
@@ -1083,8 +1085,7 @@ bool ARMFastISel::ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call) {
}
SmallVector<CCValAssign, 16> ArgLocs;
- CCState CCInfo(CC, false, TM, ArgLocs,
- I->getParent()->getParent()->getContext());
+ CCState CCInfo(CC, false, TM, ArgLocs, *Context);
CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags, CCAssignFnForCall(CC, false));
// Get a count of how many bytes are to be pushed on the stack.
@@ -1146,8 +1147,7 @@ bool ARMFastISel::ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call) {
SmallVector<unsigned, 4> UsedRegs;
if (RetVT.getSimpleVT().SimpleTy != MVT::isVoid) {
SmallVector<CCValAssign, 16> RVLocs;
- CCState CCInfo(CC, false, TM, RVLocs,
- I->getParent()->getParent()->getContext());
+ CCState CCInfo(CC, false, TM, RVLocs, *Context);
CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true));
// Copy all of the result registers out of their specified physreg.
OpenPOWER on IntegriCloud