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| author | Craig Topper <craig.topper@intel.com> | 2019-03-07 21:22:51 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2019-03-07 21:22:51 +0000 |
| commit | b3af5d3e57107a3bffe4c2d38b22ae96cee52245 (patch) | |
| tree | bcc77d1a4dad0b1279617c73665ae553bee1cd8a /llvm/lib/Target/ARM/ARMConstantIslandPass.cpp | |
| parent | 4e467043fbb5fc9c7c426019c40f9db85d84f31f (diff) | |
| download | bcm5719-llvm-b3af5d3e57107a3bffe4c2d38b22ae96cee52245.tar.gz bcm5719-llvm-b3af5d3e57107a3bffe4c2d38b22ae96cee52245.zip | |
[X86] Model ADC/SBB with immediate 0 more accurately in the Haswell scheduler model
Haswell and possibly Sandybridge have an optimization for ADC/SBB with immediate 0 to use a single uop flow. This only applies GR16/GR32/GR64 with an 8-bit immediate. It does not apply to GR8. It also does not apply to the implicit AX/EAX/RAX forms.
Differential Revision: https://reviews.llvm.org/D59058
llvm-svn: 355635
Diffstat (limited to 'llvm/lib/Target/ARM/ARMConstantIslandPass.cpp')
0 files changed, 0 insertions, 0 deletions
