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author | Sam Parker <sam.parker@arm.com> | 2019-05-09 11:56:16 +0000 |
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committer | Sam Parker <sam.parker@arm.com> | 2019-05-09 11:56:16 +0000 |
commit | d7b650cc721f7dbb52cbfa0a50797e61990d7990 (patch) | |
tree | 720a9289b3b505e542787857e9387986898efe5b /llvm/lib/Target/ARM/ARMCodeGenPrepare.cpp | |
parent | 933e305ed909fd93f9c2d7107b28e4ec2fea38ab (diff) | |
download | bcm5719-llvm-d7b650cc721f7dbb52cbfa0a50797e61990d7990.tar.gz bcm5719-llvm-d7b650cc721f7dbb52cbfa0a50797e61990d7990.zip |
[ARM][CGP] Guard against signext args and sitofp
Add an Argument that has the SExtAttr attached, as well as SIToFP
instructions, as values that generate sign bits. SIToFP doesn't
strictly do this and could be treated as a sink to be sign-extended.
Differential Revision: https://reviews.llvm.org/D61381
llvm-svn: 360331
Diffstat (limited to 'llvm/lib/Target/ARM/ARMCodeGenPrepare.cpp')
-rw-r--r-- | llvm/lib/Target/ARM/ARMCodeGenPrepare.cpp | 22 |
1 files changed, 12 insertions, 10 deletions
diff --git a/llvm/lib/Target/ARM/ARMCodeGenPrepare.cpp b/llvm/lib/Target/ARM/ARMCodeGenPrepare.cpp index b59f05d7112..93a715aa194 100644 --- a/llvm/lib/Target/ARM/ARMCodeGenPrepare.cpp +++ b/llvm/lib/Target/ARM/ARMCodeGenPrepare.cpp @@ -175,13 +175,17 @@ public: } -static bool generateSignBits(Value *V) { +static bool GenerateSignBits(Value *V) { + if (auto *Arg = dyn_cast<Argument>(V)) + return Arg->hasSExtAttr(); + if (!isa<Instruction>(V)) return false; unsigned Opc = cast<Instruction>(V)->getOpcode(); return Opc == Instruction::AShr || Opc == Instruction::SDiv || - Opc == Instruction::SRem; + Opc == Instruction::SRem || Opc == Instruction::SExt || + Opc == Instruction::SIToFP; } static bool EqualTypeSize(Value *V) { @@ -414,7 +418,7 @@ static bool isPromotedResultSafe(Value *V) { if (!isa<Instruction>(V)) return true; - if (generateSignBits(V)) + if (GenerateSignBits(V)) return false; return !isa<OverflowingBinaryOperator>(V); @@ -833,6 +837,11 @@ bool ARMCodeGenPrepare::isSupportedValue(Value *V) { return EqualTypeSize(I->getOperand(0)); } + if (GenerateSignBits(V)) { + LLVM_DEBUG(dbgs() << "ARM CGP: No, instruction can generate sign bits.\n"); + return false; + } + // Memory instructions if (isa<StoreInst>(V) || isa<GetElementPtrInst>(V)) return true; @@ -849,9 +858,6 @@ bool ARMCodeGenPrepare::isSupportedValue(Value *V) { isa<LoadInst>(V)) return isSupportedType(V); - if (isa<SExtInst>(V)) - return false; - if (auto *Cast = dyn_cast<CastInst>(V)) return isSupportedType(Cast) || isSupportedType(Cast->getOperand(0)); @@ -868,10 +874,6 @@ bool ARMCodeGenPrepare::isSupportedValue(Value *V) { if (!isSupportedType(V)) return false; - if (generateSignBits(V)) { - LLVM_DEBUG(dbgs() << "ARM CGP: No, instruction can generate sign bits.\n"); - return false; - } return true; } |