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| author | Evan Cheng <evan.cheng@apple.com> | 2008-11-08 01:44:13 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2008-11-08 01:44:13 +0000 |
| commit | 077c8f8832a90d85f0ba81988ae532aadac3ab95 (patch) | |
| tree | ea3eddc75bdeaf1a608568bf546166744c8764e6 /llvm/lib/Target/ARM/ARMCodeEmitter.cpp | |
| parent | ffdd91e3b81020c601f7d99f7f61701f4d7de4b6 (diff) | |
| download | bcm5719-llvm-077c8f8832a90d85f0ba81988ae532aadac3ab95.tar.gz bcm5719-llvm-077c8f8832a90d85f0ba81988ae532aadac3ab95.zip | |
Skip over two-address use operands.
llvm-svn: 58883
Diffstat (limited to 'llvm/lib/Target/ARM/ARMCodeEmitter.cpp')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMCodeEmitter.cpp | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/ARMCodeEmitter.cpp b/llvm/lib/Target/ARM/ARMCodeEmitter.cpp index 49d2cb0ae6e..336c04d5429 100644 --- a/llvm/lib/Target/ARM/ARMCodeEmitter.cpp +++ b/llvm/lib/Target/ARM/ARMCodeEmitter.cpp @@ -633,6 +633,8 @@ void ARMCodeEmitter::emitDataProcessingInstruction(const MachineInstr &MI, void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI, unsigned ImplicitRd, unsigned ImplicitRn) { + const TargetInstrDesc &TID = MI.getDesc(); + // Part of binary is determined by TableGn. unsigned Binary = getBinaryCodeForInstr(MI); @@ -656,6 +658,10 @@ void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI, else Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift; + // If this is a two-address operand, skip it. e.g. LDR_PRE. + if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) + ++OpIdx; + const MachineOperand &MO2 = MI.getOperand(OpIdx); unsigned AM2Opc = (ImplicitRn == ARM::PC) ? 0 : MI.getOperand(OpIdx+1).getImm(); @@ -689,6 +695,8 @@ void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI, void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI, unsigned ImplicitRn) { + const TargetInstrDesc &TID = MI.getDesc(); + // Part of binary is determined by TableGn. unsigned Binary = getBinaryCodeForInstr(MI); @@ -707,6 +715,10 @@ void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI, else Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift; + // If this is a two-address operand, skip it. e.g. LDRH_POST. + if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) + ++OpIdx; + const MachineOperand &MO2 = MI.getOperand(OpIdx); unsigned AM3Opc = (ImplicitRn == ARM::PC) ? 0 : MI.getOperand(OpIdx+1).getImm(); |

