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author | Diana Picus <diana.picus@linaro.org> | 2019-01-17 10:11:59 +0000 |
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committer | Diana Picus <diana.picus@linaro.org> | 2019-01-17 10:11:59 +0000 |
commit | 639e0661ce3d79fdf18caf351c2b335f246a13e3 (patch) | |
tree | 1c48718179c3c5fbb3e11bbc1977a9bafe4184d4 /llvm/lib/Target/ARM/ARMCallLowering.cpp | |
parent | d5c2499aecc6ab178487c8ee0376b41c6d95af54 (diff) | |
download | bcm5719-llvm-639e0661ce3d79fdf18caf351c2b335f246a13e3.tar.gz bcm5719-llvm-639e0661ce3d79fdf18caf351c2b335f246a13e3.zip |
Fix capitalization. NFC
llvm-svn: 351425
Diffstat (limited to 'llvm/lib/Target/ARM/ARMCallLowering.cpp')
-rw-r--r-- | llvm/lib/Target/ARM/ARMCallLowering.cpp | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/llvm/lib/Target/ARM/ARMCallLowering.cpp b/llvm/lib/Target/ARM/ARMCallLowering.cpp index a64544c20d1..aba0863e02b 100644 --- a/llvm/lib/Target/ARM/ARMCallLowering.cpp +++ b/llvm/lib/Target/ARM/ARMCallLowering.cpp @@ -540,19 +540,19 @@ bool ARMCallLowering::lowerCall(MachineIRBuilder &MIRBuilder, // Create the call instruction so we can add the implicit uses of arg // registers, but don't insert it yet. - bool isDirect = !Callee.isReg(); - auto CallOpcode = getCallOpcode(STI, isDirect); + bool IsDirect = !Callee.isReg(); + auto CallOpcode = getCallOpcode(STI, IsDirect); auto MIB = MIRBuilder.buildInstrNoInsert(CallOpcode); - bool isThumb = STI.isThumb(); - if (isThumb) + bool IsThumb = STI.isThumb(); + if (IsThumb) MIB.add(predOps(ARMCC::AL)); MIB.add(Callee); - if (!isDirect) { + if (!IsDirect) { auto CalleeReg = Callee.getReg(); if (CalleeReg && !TRI->isPhysicalRegister(CalleeReg)) { - unsigned CalleeIdx = isThumb ? 2 : 0; + unsigned CalleeIdx = IsThumb ? 2 : 0; MIB->getOperand(CalleeIdx).setReg(constrainOperandRegClass( MF, *TRI, MRI, *STI.getInstrInfo(), *STI.getRegBankInfo(), *MIB.getInstr(), MIB->getDesc(), Callee, CalleeIdx)); |