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| author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2011-06-16 23:31:16 +0000 |
|---|---|---|
| committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2011-06-16 23:31:16 +0000 |
| commit | 801f7ab321e5c99278741ab0a41bf22d4d5ee457 (patch) | |
| tree | 13cafaaf207b8eeece57ed2e3713a8ecee4eef26 /llvm/lib/Target/ARM/ARMBaseRegisterInfo.h | |
| parent | fa27234afbf6b7816e04eef0da1f6f8b917563f5 (diff) | |
| download | bcm5719-llvm-801f7ab321e5c99278741ab0a41bf22d4d5ee457.tar.gz bcm5719-llvm-801f7ab321e5c99278741ab0a41bf22d4d5ee457.zip | |
Rename TRI::getAllocationOrder() to getRawAllocationOrder().
Also switch the return type to ArrayRef<unsigned> which works out nicely
for ARM's implementation of this function because of the clever ArrayRef
constructors.
The name change indicates that the returned allocation order may contain
reserved registers as has been the case for a while.
llvm-svn: 133216
Diffstat (limited to 'llvm/lib/Target/ARM/ARMBaseRegisterInfo.h')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMBaseRegisterInfo.h | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h b/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h index c60d75a6893..70b6f01d6c5 100644 --- a/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h +++ b/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h @@ -134,10 +134,9 @@ public: unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const; - std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator> - getAllocationOrder(const TargetRegisterClass *RC, - unsigned HintType, unsigned HintReg, - const MachineFunction &MF) const; + ArrayRef<unsigned> getRawAllocationOrder(const TargetRegisterClass *RC, + unsigned HintType, unsigned HintReg, + const MachineFunction &MF) const; unsigned ResolveRegAllocHint(unsigned Type, unsigned Reg, const MachineFunction &MF) const; |
