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| author | Owen Anderson <resistor@mac.com> | 2011-07-21 18:54:16 +0000 |
|---|---|---|
| committer | Owen Anderson <resistor@mac.com> | 2011-07-21 18:54:16 +0000 |
| commit | b595ed0085bb3197d10bc26b0999a1b1f9751b66 (patch) | |
| tree | 466de31dcec6b98d928f1f88a17082fec7527001 /llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp | |
| parent | 49bf76bab33dfd5dffc41d22805114375d0fccbb (diff) | |
| download | bcm5719-llvm-b595ed0085bb3197d10bc26b0999a1b1f9751b66.tar.gz bcm5719-llvm-b595ed0085bb3197d10bc26b0999a1b1f9751b66.zip | |
Split up the ARM so_reg ComplexPattern into so_reg_reg and so_reg_imm, allowing us to distinguish the encodings that use shifted registers from those that use shifted immediates. This is necessary to allow the fixed-length decoder to distinguish things like BICS vs LDRH.
llvm-svn: 135693
Diffstat (limited to 'llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp index f931a58aed7..a79579e461e 100644 --- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp +++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -172,7 +172,7 @@ ARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm); unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt); UpdateMI = BuildMI(MF, MI->getDebugLoc(), - get(isSub ? ARM::SUBrs : ARM::ADDrs), WBReg) + get(isSub ? ARM::SUBrsi : ARM::ADDrsi), WBReg) .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc) .addImm(Pred).addReg(0).addReg(0); } else |
