Cleaned up the for-disassembly-only entries in the arm instruction table so that

the memory barrier variants (other than 'SY' full system domain read and write)
are treated as one instruction with option operand.

llvm-svn: 110951

1 files changed, 9 insertions, 0 deletions

diff --git a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
index b09cd73176d..ded9800052e 100644
--- a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
+++ b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
@@ -122,6 +122,8 @@ namespace {
                                 const char *Modifier = 0);
     void printBitfieldInvMaskImmOperand(const MachineInstr *MI, int OpNum,
                                         raw_ostream &O);
+    void printMemBOption(const MachineInstr *MI, int OpNum,
+                         raw_ostream &O);
     void printSatShiftOperand(const MachineInstr *MI, int OpNum,
                               raw_ostream &O);
 
@@ -671,6 +673,13 @@ ARMAsmPrinter::printBitfieldInvMaskImmOperand(const MachineInstr *MI, int Op,
   O << "#" << lsb << ", #" << width;
 }
 
+void
+ARMAsmPrinter::printMemBOption(const MachineInstr *MI, int OpNum,
+                               raw_ostream &O) {
+  unsigned val = MI->getOperand(OpNum).getImm();
+  O << ARM_MB::MemBOptToString(val);
+}
+
 void ARMAsmPrinter::printSatShiftOperand(const MachineInstr *MI, int OpNum,
                                          raw_ostream &O) {
   unsigned ShiftOp = MI->getOperand(OpNum).getImm();