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| author | Diana Picus <diana.picus@linaro.org> | 2017-05-02 09:40:49 +0000 |
|---|---|---|
| committer | Diana Picus <diana.picus@linaro.org> | 2017-05-02 09:40:49 +0000 |
| commit | 8abcbbb24bd3dabfce0c7476882cbddcee39c2e9 (patch) | |
| tree | 1cd33e44fef0d165050c695598a20288c4842f45 /llvm/lib/Target/ARM/ARM.h | |
| parent | b7101479a899f7b1da92b1c1e956394e43789c0a (diff) | |
| download | bcm5719-llvm-8abcbbb24bd3dabfce0c7476882cbddcee39c2e9.tar.gz bcm5719-llvm-8abcbbb24bd3dabfce0c7476882cbddcee39c2e9.zip | |
[ARM] GlobalISel: Use TableGen instruction selector
Emit and use the TableGen instruction selector for ARM. At the moment,
this allows us to remove the hand-written code for selecting G_SDIV and
G_UDIV.
Future commits will focus on increasing the code coverage for it and
removing more dead code from the current instruction selector.
llvm-svn: 301905
Diffstat (limited to 'llvm/lib/Target/ARM/ARM.h')
| -rw-r--r-- | llvm/lib/Target/ARM/ARM.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/ARM.h b/llvm/lib/Target/ARM/ARM.h index 8d136edc262..4676226acd9 100644 --- a/llvm/lib/Target/ARM/ARM.h +++ b/llvm/lib/Target/ARM/ARM.h @@ -47,7 +47,7 @@ FunctionPass *createARMOptimizeBarriersPass(); FunctionPass *createThumb2SizeReductionPass( std::function<bool(const Function &)> Ftor = nullptr); InstructionSelector * -createARMInstructionSelector(const ARMSubtarget &STI, +createARMInstructionSelector(const ARMBaseTargetMachine &TM, const ARMSubtarget &STI, const ARMRegisterBankInfo &RBI); void LowerARMMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI, |
