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| author | Dimitry Andric <dimitry@andric.com> | 2017-12-18 19:46:56 +0000 |
|---|---|---|
| committer | Dimitry Andric <dimitry@andric.com> | 2017-12-18 19:46:56 +0000 |
| commit | e4f5d010330159a919c0fa0fc0c769f12a17a00d (patch) | |
| tree | 547cd449894a83ffaa5d0483c5ab0c6fa66dce05 /llvm/lib/Target/ARC | |
| parent | 48176a5fb6d409ce394052145cd3ad5449ae51b6 (diff) | |
| download | bcm5719-llvm-e4f5d010330159a919c0fa0fc0c769f12a17a00d.tar.gz bcm5719-llvm-e4f5d010330159a919c0fa0fc0c769f12a17a00d.zip | |
Fix more inconsistent line endings. NFC.
llvm-svn: 321016
Diffstat (limited to 'llvm/lib/Target/ARC')
| -rw-r--r-- | llvm/lib/Target/ARC/ARCInstrFormats.td | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/ARC/ARCInstrInfo.td | 14 |
2 files changed, 8 insertions, 8 deletions
diff --git a/llvm/lib/Target/ARC/ARCInstrFormats.td b/llvm/lib/Target/ARC/ARCInstrFormats.td index bddef6b9500..50edddd4ea9 100644 --- a/llvm/lib/Target/ARC/ARCInstrFormats.td +++ b/llvm/lib/Target/ARC/ARCInstrFormats.td @@ -29,7 +29,7 @@ class immS<int BSz> : Operand<i32>, PatLeaf<(imm), let DecoderMethod = "DecodeSignedOperand<"#BSz#">"; } -// e.g. s3 field may encode the signed integers values -1 .. 6
+// e.g. s3 field may encode the signed integers values -1 .. 6 // using binary codes 111, 000, 001, 010, 011, 100, 101, and 110, respectively class immC<int BSz> : Operand<i32>, PatLeaf<(imm), "\n return isInt<"#BSz#">(N->getSExtValue());"> { diff --git a/llvm/lib/Target/ARC/ARCInstrInfo.td b/llvm/lib/Target/ARC/ARCInstrInfo.td index e4ad162edee..edd853fe150 100644 --- a/llvm/lib/Target/ARC/ARCInstrInfo.td +++ b/llvm/lib/Target/ARC/ARCInstrInfo.td @@ -534,13 +534,13 @@ let isBranch = 1 in { def BEQ_S : F16_BCC_s10<0b01, "beq_s">; def BNE_S : F16_BCC_s10<0b10, "bne_s">; - def BGT_S : F16_BCC_s7<0b000, "bgt_s">;
- def BGE_S : F16_BCC_s7<0b001, "bge_s">;
- def BLT_S : F16_BCC_s7<0b010, "blt_s">;
- def BLE_S : F16_BCC_s7<0b011, "ble_s">;
- def BHI_S : F16_BCC_s7<0b100, "bhi_s">;
- def BHS_S : F16_BCC_s7<0b101, "bhs_s">;
- def BLO_S : F16_BCC_s7<0b110, "blo_s">;
+ def BGT_S : F16_BCC_s7<0b000, "bgt_s">; + def BGE_S : F16_BCC_s7<0b001, "bge_s">; + def BLT_S : F16_BCC_s7<0b010, "blt_s">; + def BLE_S : F16_BCC_s7<0b011, "ble_s">; + def BHI_S : F16_BCC_s7<0b100, "bhi_s">; + def BHS_S : F16_BCC_s7<0b101, "bhs_s">; + def BLO_S : F16_BCC_s7<0b110, "blo_s">; def BLS_S : F16_BCC_s7<0b111, "bls_s">; } // let isBranch |

