summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/ARC
diff options
context:
space:
mode:
authorPeter Collingbourne <peter@pcc.me.uk>2018-05-17 20:46:01 +0000
committerPeter Collingbourne <peter@pcc.me.uk>2018-05-17 20:46:01 +0000
commit0d8fa1b6fda2acf85f01ec550781ccd70a547967 (patch)
tree100efd49240af39e425bcdaca4b62ddbb08cf43a /llvm/lib/Target/ARC
parent5a668a054bddcc5472b0bdfa025713caca5bde38 (diff)
downloadbcm5719-llvm-0d8fa1b6fda2acf85f01ec550781ccd70a547967.tar.gz
bcm5719-llvm-0d8fa1b6fda2acf85f01ec550781ccd70a547967.zip
ARC, Nios2: Silence build warnings. NFCI.
llvm-svn: 332663
Diffstat (limited to 'llvm/lib/Target/ARC')
-rw-r--r--llvm/lib/Target/ARC/ARCISelLowering.cpp2
-rw-r--r--llvm/lib/Target/ARC/ARCISelLowering.h1
-rw-r--r--llvm/lib/Target/ARC/ARCMachineFunctionInfo.h5
-rw-r--r--llvm/lib/Target/ARC/InstPrinter/ARCInstPrinter.cpp3
4 files changed, 4 insertions, 7 deletions
diff --git a/llvm/lib/Target/ARC/ARCISelLowering.cpp b/llvm/lib/Target/ARC/ARCISelLowering.cpp
index 0ec953f341a..bf98af80140 100644
--- a/llvm/lib/Target/ARC/ARCISelLowering.cpp
+++ b/llvm/lib/Target/ARC/ARCISelLowering.cpp
@@ -72,7 +72,7 @@ static ARCCC::CondCode ISDCCtoARCCC(ISD::CondCode isdCC) {
ARCTargetLowering::ARCTargetLowering(const TargetMachine &TM,
const ARCSubtarget &Subtarget)
- : TargetLowering(TM), TM(TM), Subtarget(Subtarget) {
+ : TargetLowering(TM), Subtarget(Subtarget) {
// Set up the register classes.
addRegisterClass(MVT::i32, &ARC::GPR32RegClass);
diff --git a/llvm/lib/Target/ARC/ARCISelLowering.h b/llvm/lib/Target/ARC/ARCISelLowering.h
index cb06e9dcd79..fec01b13a86 100644
--- a/llvm/lib/Target/ARC/ARCISelLowering.h
+++ b/llvm/lib/Target/ARC/ARCISelLowering.h
@@ -76,7 +76,6 @@ public:
Instruction *I = nullptr) const override;
private:
- const TargetMachine &TM;
const ARCSubtarget &Subtarget;
// Lower Operand helpers
diff --git a/llvm/lib/Target/ARC/ARCMachineFunctionInfo.h b/llvm/lib/Target/ARC/ARCMachineFunctionInfo.h
index bfb3fdef5eb..95ad294e366 100644
--- a/llvm/lib/Target/ARC/ARCMachineFunctionInfo.h
+++ b/llvm/lib/Target/ARC/ARCMachineFunctionInfo.h
@@ -25,16 +25,15 @@ class ARCFunctionInfo : public MachineFunctionInfo {
virtual void anchor();
bool ReturnStackOffsetSet;
int VarArgsFrameIndex;
- unsigned VarArgFrameBytes;
unsigned ReturnStackOffset;
public:
ARCFunctionInfo()
- : ReturnStackOffsetSet(false), VarArgsFrameIndex(0), VarArgFrameBytes(0),
+ : ReturnStackOffsetSet(false), VarArgsFrameIndex(0),
ReturnStackOffset(-1U), MaxCallStackReq(0) {}
explicit ARCFunctionInfo(MachineFunction &MF)
- : ReturnStackOffsetSet(false), VarArgsFrameIndex(0), VarArgFrameBytes(0),
+ : ReturnStackOffsetSet(false), VarArgsFrameIndex(0),
ReturnStackOffset(-1U), MaxCallStackReq(0) {
// Functions are 4-byte (2**2) aligned.
MF.setAlignment(2);
diff --git a/llvm/lib/Target/ARC/InstPrinter/ARCInstPrinter.cpp b/llvm/lib/Target/ARC/InstPrinter/ARCInstPrinter.cpp
index 48431677bb7..0c627d04698 100644
--- a/llvm/lib/Target/ARC/InstPrinter/ARCInstPrinter.cpp
+++ b/llvm/lib/Target/ARC/InstPrinter/ARCInstPrinter.cpp
@@ -43,9 +43,8 @@ static const char *ARCBRCondCodeToString(ARCCC::BRCondCode BRCC) {
return "lo";
case ARCCC::BRHS:
return "hs";
- default:
- llvm_unreachable("Unhandled ARCCC::BRCondCode");
}
+ llvm_unreachable("Unhandled ARCCC::BRCondCode");
}
static const char *ARCCondCodeToString(ARCCC::CondCode CC) {
OpenPOWER on IntegriCloud