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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2015-09-24 07:51:23 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2015-09-24 07:51:23 +0000 |
| commit | fa242960fc28f433f2fe4eecbe87dd4ebb569524 (patch) | |
| tree | 0d79708205631633a9a97430810e8101afd7ea50 /llvm/lib/Target/AMDGPU | |
| parent | b12c0d9e3874506272b20b7504f7fd831754e7f7 (diff) | |
| download | bcm5719-llvm-fa242960fc28f433f2fe4eecbe87dd4ebb569524.tar.gz bcm5719-llvm-fa242960fc28f433f2fe4eecbe87dd4ebb569524.zip | |
AMDGPU: Add readonly to InstrMapping functions
llvm-svn: 248474
Diffstat (limited to 'llvm/lib/Target/AMDGPU')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIInstrInfo.h | 16 |
1 files changed, 15 insertions, 1 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.h b/llvm/lib/Target/AMDGPU/SIInstrInfo.h index 9b4ba029122..272b65104a8 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.h +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.h @@ -113,6 +113,8 @@ public: // register. If there is no hardware instruction that can store to \p // DstRC, then AMDGPU::COPY is returned. unsigned getMovOpcode(const TargetRegisterClass *DstRC) const; + + LLVM_READONLY int commuteOpcode(const MachineInstr &MI) const; MachineInstr *commuteInstruction(MachineInstr *MI, @@ -348,13 +350,25 @@ public: }; namespace AMDGPU { - + LLVM_READONLY int getVOPe64(uint16_t Opcode); + + LLVM_READONLY int getVOPe32(uint16_t Opcode); + + LLVM_READONLY int getCommuteRev(uint16_t Opcode); + + LLVM_READONLY int getCommuteOrig(uint16_t Opcode); + + LLVM_READONLY int getAddr64Inst(uint16_t Opcode); + + LLVM_READONLY int getAtomicRetOp(uint16_t Opcode); + + LLVM_READONLY int getAtomicNoRetOp(uint16_t Opcode); const uint64_t RSRC_DATA_FORMAT = 0xf00000000000LL; |
