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| author | Farhana Aleen <farhana.aleen@gmail.com> | 2018-04-03 23:00:30 +0000 |
|---|---|---|
| committer | Farhana Aleen <farhana.aleen@gmail.com> | 2018-04-03 23:00:30 +0000 |
| commit | e80aeac0f2f5fce6e986307a8b69d8a44b402b4e (patch) | |
| tree | 076685aa638ec2ae7b45aa751a34163e69dde00a /llvm/lib/Target/AMDGPU | |
| parent | 6b8d8f401089a578b8687f2335ed7b321cd89db3 (diff) | |
| download | bcm5719-llvm-e80aeac0f2f5fce6e986307a8b69d8a44b402b4e.tar.gz bcm5719-llvm-e80aeac0f2f5fce6e986307a8b69d8a44b402b4e.zip | |
[AMDGPU] performMinMaxCombine should not optimize patterns of vectors to min3/max3.
Summary: There are no packed instructions for min3 or max3. So, performMinMaxCombine should not optimize vectors of f16 to min3/max3.
Author: FarhanaAleen
Reviewed By: arsenm
Subscribers: llvm-commits, AMDGPU
Differential Revision: https://reviews.llvm.org/D45219
llvm-svn: 329131
Diffstat (limited to 'llvm/lib/Target/AMDGPU')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index f0d5e926e3c..2a7549ed77f 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -6446,7 +6446,7 @@ SDValue SITargetLowering::performMinMaxCombine(SDNode *N, if (Opc != AMDGPUISD::FMIN_LEGACY && Opc != AMDGPUISD::FMAX_LEGACY && - VT != MVT::f64 && + !VT.isVector() && VT != MVT::f64 && ((VT != MVT::f16 && VT != MVT::i16) || Subtarget->hasMin3Max3_16())) { // max(max(a, b), c) -> max3(a, b, c) // min(min(a, b), c) -> min3(a, b, c) |
