AMDGPU: Swap order of operands in fadd/fsub combine

FMA is canonicalized to constant in the middle operand. Do
the same so fmad matches and avoid an extra combine step.

llvm-svn: 290313

1 files changed, 4 insertions, 4 deletions

diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 9a0002d9b0d..eddec320c02 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -3917,7 +3917,7 @@ SDValue SITargetLowering::performFAddCombine(SDNode *N,
       unsigned FusedOp = getFusedOpcode(DAG, N, LHS.getNode());
       if (FusedOp != 0) {
         const SDValue Two = DAG.getConstantFP(2.0, SL, VT);
-        return DAG.getNode(FusedOp, SL, VT, Two, A, RHS);
+        return DAG.getNode(FusedOp, SL, VT, A, Two, RHS);
       }
     }
   }
@@ -3929,7 +3929,7 @@ SDValue SITargetLowering::performFAddCombine(SDNode *N,
       unsigned FusedOp = getFusedOpcode(DAG, N, RHS.getNode());
       if (FusedOp != 0) {
         const SDValue Two = DAG.getConstantFP(2.0, SL, VT);
-        return DAG.getNode(FusedOp, SL, VT, Two, A, LHS);
+        return DAG.getNode(FusedOp, SL, VT, A, Two, LHS);
       }
     }
   }
@@ -3963,7 +3963,7 @@ SDValue SITargetLowering::performFSubCombine(SDNode *N,
         const SDValue Two = DAG.getConstantFP(2.0, SL, VT);
         SDValue NegRHS = DAG.getNode(ISD::FNEG, SL, VT, RHS);
 
-        return DAG.getNode(FusedOp, SL, VT, Two, A, NegRHS);
+        return DAG.getNode(FusedOp, SL, VT, A, Two, NegRHS);
       }
     }
   }
@@ -3976,7 +3976,7 @@ SDValue SITargetLowering::performFSubCombine(SDNode *N,
       unsigned FusedOp = getFusedOpcode(DAG, N, RHS.getNode());
       if (FusedOp != 0){
         const SDValue NegTwo = DAG.getConstantFP(-2.0, SL, VT);
-        return DAG.getNode(FusedOp, SL, VT, NegTwo, A, LHS);
+        return DAG.getNode(FusedOp, SL, VT, A, NegTwo, LHS);
       }
     }
   }