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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2015-09-24 07:51:28 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2015-09-24 07:51:28 +0000 |
| commit | e068f9a263a6b49fab08adcd70aa979caed5b76f (patch) | |
| tree | 27f985daed7ee771f66b110b045231894905cea4 /llvm/lib/Target/AMDGPU | |
| parent | 708586faa23d07aba2423f2c0133f6eab4f3e6ec (diff) | |
| download | bcm5719-llvm-e068f9a263a6b49fab08adcd70aa979caed5b76f.tar.gz bcm5719-llvm-e068f9a263a6b49fab08adcd70aa979caed5b76f.zip | |
AMDGPU: Return after instruction is processed.
llvm-svn: 248476
Diffstat (limited to 'llvm/lib/Target/AMDGPU')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp index f021e0fd4fe..f40cd0cdeb7 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp @@ -1730,6 +1730,8 @@ void SIInstrInfo::legalizeOperands(MachineInstr *MI) const { // legalize it. legalizeOpWithMove(MI, Idx); } + + return; } // Legalize REG_SEQUENCE and PHI @@ -1785,6 +1787,8 @@ void SIInstrInfo::legalizeOperands(MachineInstr *MI) const { .addOperand(MI->getOperand(i)); MI->getOperand(i).setReg(DstReg); } + + return; } // Legalize INSERT_SUBREG |
