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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-10-10 20:34:49 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-10-10 20:34:49 +0000 |
| commit | d674e0ac0d36d74a91f4ce70e5bc50805c7d2c39 (patch) | |
| tree | d61e31c44e1c6e619cd6027e82bc040fa54d7997 /llvm/lib/Target/AMDGPU | |
| parent | 3a3ba77ba3e9d421eccf66e69d1138d96d43a3d5 (diff) | |
| download | bcm5719-llvm-d674e0ac0d36d74a91f4ce70e5bc50805c7d2c39.tar.gz bcm5719-llvm-d674e0ac0d36d74a91f4ce70e5bc50805c7d2c39.zip | |
AMDGPU: Fix failure to select branch with optnone
opt-bisect/optnone disable the AMDGPUUniformAnnotateValues pass.
The heuristic in the custom selector for brcond deferred the
branch uniformity check to the pattern, which would fail.
llvm-svn: 315360
Diffstat (limited to 'llvm/lib/Target/AMDGPU')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp | 13 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIInstrInfo.td | 10 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SOPInstructions.td | 3 |
3 files changed, 6 insertions, 20 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp index 1537c359792..b74b2c216b5 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp @@ -1645,16 +1645,13 @@ void AMDGPUDAGToDAGISel::SelectBRCOND(SDNode *N) { return; } - if (isCBranchSCC(N)) { - // This brcond will use S_CBRANCH_SCC*, so let tablegen handle it. - SelectCode(N); - return; - } - + bool UseSCCBr = isCBranchSCC(N) && isUniformBr(N); + unsigned BrOp = UseSCCBr ? AMDGPU::S_CBRANCH_SCC1 : AMDGPU::S_CBRANCH_VCCNZ; + unsigned CondReg = UseSCCBr ? AMDGPU::SCC : AMDGPU::VCC; SDLoc SL(N); - SDValue VCC = CurDAG->getCopyToReg(N->getOperand(0), SL, AMDGPU::VCC, Cond); - CurDAG->SelectNodeTo(N, AMDGPU::S_CBRANCH_VCCNZ, MVT::Other, + SDValue VCC = CurDAG->getCopyToReg(N->getOperand(0), SL, CondReg, Cond); + CurDAG->SelectNodeTo(N, BrOp, MVT::Other, N->getOperand(2), // Basic Block VCC.getValue(0)); } diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.td b/llvm/lib/Target/AMDGPU/SIInstrInfo.td index c0a844e255c..7418a2bd902 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.td +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.td @@ -232,16 +232,6 @@ def si_setcc_uniform : PatFrag < return true; }]>; -def si_uniform_br : PatFrag < - (ops node:$cond, node:$bb), (brcond node:$cond, node:$bb), [{ - return isUniformBr(N); -}]>; - -def si_uniform_br_scc : PatFrag < - (ops node:$cond, node:$bb), (si_uniform_br node:$cond, node:$bb), [{ - return isCBranchSCC(N); -}]>; - def lshr_rev : PatFrag < (ops node:$src1, node:$src0), (srl $src0, $src1) diff --git a/llvm/lib/Target/AMDGPU/SOPInstructions.td b/llvm/lib/Target/AMDGPU/SOPInstructions.td index 43c54875944..49e4bf07c81 100644 --- a/llvm/lib/Target/AMDGPU/SOPInstructions.td +++ b/llvm/lib/Target/AMDGPU/SOPInstructions.td @@ -817,8 +817,7 @@ def S_CBRANCH_SCC0 : SOPP < >; def S_CBRANCH_SCC1 : SOPP < 0x00000005, (ins sopp_brtarget:$simm16), - "s_cbranch_scc1 $simm16", - [(si_uniform_br_scc SCC, bb:$simm16)] + "s_cbranch_scc1 $simm16" >; } // End Uses = [SCC] |
