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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-06-09 23:19:08 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-06-09 23:19:08 +0000 |
| commit | cfb61e780abb39e025a2b7209b273bc5aa124f8a (patch) | |
| tree | cd64eb83a039490736b0982755148ab9cb316d73 /llvm/lib/Target/AMDGPU | |
| parent | c3a01ec9db251271324c340e2ee44db1faa9dedf (diff) | |
| download | bcm5719-llvm-cfb61e780abb39e025a2b7209b273bc5aa124f8a.tar.gz bcm5719-llvm-cfb61e780abb39e025a2b7209b273bc5aa124f8a.zip | |
AMDGPU: Remove incorrect assertion
I'm still not sure under what circumstances the offset here is non-0,
but private memory is not limited to 27-bits.
llvm-svn: 272337
Diffstat (limited to 'llvm/lib/Target/AMDGPU')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp index 477792da7bf..c7cb88a77a0 100644 --- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp @@ -277,10 +277,6 @@ void SIRegisterInfo::materializeFrameBaseRegister(MachineBasicBlock *MBB, const AMDGPUSubtarget &Subtarget = MF->getSubtarget<AMDGPUSubtarget>(); const TargetInstrInfo *TII = Subtarget.getInstrInfo(); - assert(isUInt<27>(Offset) && - "Private offset should never exceed maximum private size"); - - if (Offset == 0) { BuildMI(*MBB, Ins, DL, TII->get(AMDGPU::V_MOV_B32_e32), BaseReg) .addFrameIndex(FrameIdx); |
