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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2018-08-06 21:51:52 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2018-08-06 21:51:52 +0000 |
| commit | ce6d61fba83d926c8dfacedae4d25c44e28ab893 (patch) | |
| tree | 557830c22f581d5c92fe2ba659fa506bb70e74c5 /llvm/lib/Target/AMDGPU | |
| parent | ddbabc6b7c3fc401d7b59f4c905c5964cb3c5643 (diff) | |
| download | bcm5719-llvm-ce6d61fba83d926c8dfacedae4d25c44e28ab893.tar.gz bcm5719-llvm-ce6d61fba83d926c8dfacedae4d25c44e28ab893.zip | |
AMDGPU: Conversions always produce canonical results
Not sure why this was checking for denormals for f16.
My interpretation of the IEEE standard is conversions
should produce a canonical result, and the ISA manual
says denormals are created when appropriate.
llvm-svn: 339064
Diffstat (limited to 'llvm/lib/Target/AMDGPU')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 9 |
1 files changed, 2 insertions, 7 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index 22d33f568e8..c598c6d69cc 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -6775,16 +6775,11 @@ bool SITargetLowering::isCanonicalized(SelectionDAG &DAG, SDValue Op, case ISD::FSQRT: case ISD::FDIV: case ISD::FREM: + case ISD::FP_ROUND: + case ISD::FP_EXTEND: case AMDGPUISD::FMUL_LEGACY: case AMDGPUISD::FMAD_FTZ: return true; - case ISD::FP_ROUND: - return Op.getValueType().getScalarType() != MVT::f16 || - Subtarget->hasFP16Denormals(); - - case ISD::FP_EXTEND: - return Op.getOperand(0).getValueType().getScalarType() != MVT::f16 || - Subtarget->hasFP16Denormals(); // It can/will be lowered or combined as a bit operation. // Need to check their input recursively to handle. |

