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| author | Chad Rosier <mcrosier@codeaurora.org> | 2016-03-09 16:00:35 +0000 |
|---|---|---|
| committer | Chad Rosier <mcrosier@codeaurora.org> | 2016-03-09 16:00:35 +0000 |
| commit | c27a18f39fa155583a5a124549137016cb8c7712 (patch) | |
| tree | f316fd4a7f4422f6817d9472287c4011b9a083a9 /llvm/lib/Target/AMDGPU | |
| parent | 069b432bf7357b680384f4a90b596c8b9cb2c343 (diff) | |
| download | bcm5719-llvm-c27a18f39fa155583a5a124549137016cb8c7712.tar.gz bcm5719-llvm-c27a18f39fa155583a5a124549137016cb8c7712.zip | |
[TII] Allow getMemOpBaseRegImmOfs() to accept negative offsets. NFC.
http://reviews.llvm.org/D17967
llvm-svn: 263021
Diffstat (limited to 'llvm/lib/Target/AMDGPU')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 6 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIInstrInfo.h | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp | 3 |
3 files changed, 6 insertions, 5 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp index bbc19fdc715..f3dfde7e104 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp @@ -202,7 +202,7 @@ static bool isStride64(unsigned Opc) { } bool SIInstrInfo::getMemOpBaseRegImmOfs(MachineInstr *LdSt, unsigned &BaseReg, - unsigned &Offset, + int64_t &Offset, const TargetRegisterInfo *TRI) const { unsigned Opc = LdSt->getOpcode(); @@ -1160,8 +1160,8 @@ static bool offsetsDoNotOverlap(int WidthA, int OffsetA, bool SIInstrInfo::checkInstOffsetsDoNotOverlap(MachineInstr *MIa, MachineInstr *MIb) const { - unsigned BaseReg0, Offset0; - unsigned BaseReg1, Offset1; + unsigned BaseReg0, BaseReg1; + int64_t Offset0, Offset1; if (getMemOpBaseRegImmOfs(MIa, BaseReg0, Offset0, &RI) && getMemOpBaseRegImmOfs(MIb, BaseReg1, Offset1, &RI)) { diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.h b/llvm/lib/Target/AMDGPU/SIInstrInfo.h index 3a96d79c1d7..f0c3d10b8bc 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.h +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.h @@ -91,7 +91,7 @@ public: int64_t &Offset2) const override; bool getMemOpBaseRegImmOfs(MachineInstr *LdSt, unsigned &BaseReg, - unsigned &Offset, + int64_t &Offset, const TargetRegisterInfo *TRI) const final; bool shouldClusterLoads(MachineInstr *FirstLdSt, diff --git a/llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp b/llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp index cd399333485..5ef12e7f5ea 100644 --- a/llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp +++ b/llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp @@ -1879,7 +1879,8 @@ void SIScheduleDAGMI::schedule() for (unsigned i = 0, e = (unsigned)SUnits.size(); i != e; ++i) { SUnit *SU = &SUnits[i]; - unsigned BaseLatReg, OffLatReg; + unsigned BaseLatReg; + int64_t OffLatReg; if (SITII->isLowLatencyInstruction(SU->getInstr())) { IsLowLatencySU[i] = 1; if (SITII->getMemOpBaseRegImmOfs(SU->getInstr(), BaseLatReg, |
