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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2020-01-12 19:12:59 -0500 |
|---|---|---|
| committer | Matt Arsenault <arsenm2@gmail.com> | 2020-01-12 22:44:51 -0500 |
| commit | a10527cd3731e2ef246c4797fb099385a948f62f (patch) | |
| tree | ba1ec74f1e974151489e3a693989362eb283d90b /llvm/lib/Target/AMDGPU | |
| parent | 79a09d8bf4d508b0ae6a1e3c90907488092678c5 (diff) | |
| download | bcm5719-llvm-a10527cd3731e2ef246c4797fb099385a948f62f.tar.gz bcm5719-llvm-a10527cd3731e2ef246c4797fb099385a948f62f.zip | |
AMDGPU/GlobalISel: Copy type when inserting readfirstlane
getDefIgnoringCopies will fail to find any def if no type is set if we
try to use it on the use's operand, so propagate the type.
Diffstat (limited to 'llvm/lib/Target/AMDGPU')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp index dbc75a62254..40da3934ec2 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp @@ -1090,6 +1090,8 @@ void AMDGPURegisterBankInfo::constrainOpWithReadfirstlane( .addDef(SGPR) .addReg(Reg); + MRI.setType(SGPR, MRI.getType(Reg)); + const TargetRegisterClass *Constrained = constrainGenericRegister(Reg, AMDGPU::VGPR_32RegClass, MRI); (void)Constrained; |
