diff options
| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2020-01-07 20:22:06 -0500 |
|---|---|---|
| committer | Matt Arsenault <arsenm2@gmail.com> | 2020-01-09 10:29:32 -0500 |
| commit | 9ffd0ed838191247e0da7df5e28e54a5129e76a7 (patch) | |
| tree | d5cd6686d07f75b943136774750d3eefe0b5c643 /llvm/lib/Target/AMDGPU | |
| parent | c66b2e1c87ecde72eb37d3452ec9c1b8766ede30 (diff) | |
| download | bcm5719-llvm-9ffd0ed838191247e0da7df5e28e54a5129e76a7.tar.gz bcm5719-llvm-9ffd0ed838191247e0da7df5e28e54a5129e76a7.zip | |
AMDGPU/GlobalISel: Fix import of integer med3
This isn't too useful now, since nothing is currently trying to form
min/max from cmp+select.
Diffstat (limited to 'llvm/lib/Target/AMDGPU')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPUInstructions.td | 24 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIInstructions.td | 38 |
2 files changed, 30 insertions, 32 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td b/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td index 6541470f06a..7e71dbdd124 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td +++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td @@ -737,30 +737,6 @@ class ROTRPattern <Instruction BIT_ALIGN> : AMDGPUPat < (BIT_ALIGN $src0, $src0, $src1) >; -multiclass IntMed3Pat<Instruction med3Inst, - SDPatternOperator min, - SDPatternOperator max, - SDPatternOperator min_oneuse, - SDPatternOperator max_oneuse, - ValueType vt = i32> { - - // This matches 16 permutations of - // min(max(a, b), max(min(a, b), c)) - def : AMDGPUPat < - (min (max_oneuse vt:$src0, vt:$src1), - (max_oneuse (min_oneuse vt:$src0, vt:$src1), vt:$src2)), - (med3Inst vt:$src0, vt:$src1, vt:$src2) ->; - - // This matches 16 permutations of - // max(min(x, y), min(max(x, y), z)) - def : AMDGPUPat < - (max (min_oneuse vt:$src0, vt:$src1), - (min_oneuse (max_oneuse vt:$src0, vt:$src1), vt:$src2)), - (med3Inst $src0, $src1, $src2) ->; -} - // Special conversion patterns def cvt_rpi_i32_f32 : PatFrag < diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td index 4c8197975ce..d84720f820e 100644 --- a/llvm/lib/Target/AMDGPU/SIInstructions.td +++ b/llvm/lib/Target/AMDGPU/SIInstructions.td @@ -1972,6 +1972,29 @@ defm : BFMPatterns <i32, S_BFM_B32, S_MOV_B32>; defm : BFEPattern <V_BFE_U32, V_BFE_I32, S_MOV_B32>; defm : SHA256MaPattern <V_BFI_B32, V_XOR_B32_e64, SReg_64>; +multiclass IntMed3Pat<Instruction med3Inst, + SDPatternOperator min, + SDPatternOperator max, + SDPatternOperator min_oneuse, + SDPatternOperator max_oneuse> { + + // This matches 16 permutations of + // min(max(a, b), max(min(a, b), c)) + def : AMDGPUPat < + (min (max_oneuse i32:$src0, i32:$src1), + (max_oneuse (min_oneuse i32:$src0, i32:$src1), i32:$src2)), + (med3Inst VSrc_b32:$src0, VSrc_b32:$src1, VSrc_b32:$src2) +>; + + // This matches 16 permutations of + // max(min(x, y), min(max(x, y), z)) + def : AMDGPUPat < + (max (min_oneuse i32:$src0, i32:$src1), + (min_oneuse (max_oneuse i32:$src0, i32:$src1), i32:$src2)), + (med3Inst VSrc_b32:$src0, VSrc_b32:$src1, VSrc_b32:$src2) +>; +} + defm : IntMed3Pat<V_MED3_I32, smin, smax, smin_oneuse, smax_oneuse>; defm : IntMed3Pat<V_MED3_U32, umin, umax, umin_oneuse, umax_oneuse>; @@ -2002,22 +2025,21 @@ multiclass Int16Med3Pat<Instruction med3Inst, SDPatternOperator min, SDPatternOperator max, SDPatternOperator max_oneuse, - SDPatternOperator min_oneuse, - ValueType vt = i16> { + SDPatternOperator min_oneuse> { // This matches 16 permutations of // max(min(x, y), min(max(x, y), z)) def : GCNPat < - (max (min_oneuse vt:$src0, vt:$src1), - (min_oneuse (max_oneuse vt:$src0, vt:$src1), vt:$src2)), - (med3Inst SRCMODS.NONE, $src0, SRCMODS.NONE, $src1, SRCMODS.NONE, $src2, DSTCLAMP.NONE) + (max (min_oneuse i16:$src0, i16:$src1), + (min_oneuse (max_oneuse i16:$src0, i16:$src1), i16:$src2)), + (med3Inst SRCMODS.NONE, VSrc_b16:$src0, SRCMODS.NONE, VSrc_b16:$src1, SRCMODS.NONE, VSrc_b16:$src2, DSTCLAMP.NONE) >; // This matches 16 permutations of // min(max(a, b), max(min(a, b), c)) def : GCNPat < - (min (max_oneuse vt:$src0, vt:$src1), - (max_oneuse (min_oneuse vt:$src0, vt:$src1), vt:$src2)), - (med3Inst SRCMODS.NONE, $src0, SRCMODS.NONE, $src1, SRCMODS.NONE, $src2, DSTCLAMP.NONE) + (min (max_oneuse i16:$src0, i16:$src1), + (max_oneuse (min_oneuse i16:$src0, i16:$src1), i16:$src2)), + (med3Inst SRCMODS.NONE, VSrc_b16:$src0, SRCMODS.NONE, VSrc_b16:$src1, SRCMODS.NONE, VSrc_b16:$src2, DSTCLAMP.NONE) >; } |

