diff options
| author | Krzysztof Parzyszek <kparzysz@codeaurora.org> | 2016-12-15 14:36:06 +0000 |
|---|---|---|
| committer | Krzysztof Parzyszek <kparzysz@codeaurora.org> | 2016-12-15 14:36:06 +0000 |
| commit | 91b5cf8412a9fffdca96619f02f485c8c48bf852 (patch) | |
| tree | 45cc792752ed1bae1559f8501bc5e485eda07fed /llvm/lib/Target/AMDGPU | |
| parent | 2f7f0e7a480d760999f1973d8db76aee590cf83e (diff) | |
| download | bcm5719-llvm-91b5cf8412a9fffdca96619f02f485c8c48bf852.tar.gz bcm5719-llvm-91b5cf8412a9fffdca96619f02f485c8c48bf852.zip | |
Extract LaneBitmask into a separate type
Specifically avoid implicit conversions from/to integral types to
avoid potential errors when changing the underlying type. For example,
a typical initialization of a "full" mask was "LaneMask = ~0u", which
would result in a value of 0x00000000FFFFFFFF if the type was extended
to uint64_t.
Differential Revision: https://reviews.llvm.org/D27454
llvm-svn: 289820
Diffstat (limited to 'llvm/lib/Target/AMDGPU')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp index bda0a44c984..8c4b24a4504 100644 --- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp @@ -1027,7 +1027,8 @@ const TargetRegisterClass *SIRegisterInfo::getSubRegClass( return RC; // We can assume that each lane corresponds to one 32-bit register. - unsigned Count = countPopulation(getSubRegIndexLaneMask(SubIdx)); + LaneBitmask::Type Mask = getSubRegIndexLaneMask(SubIdx).getAsInteger(); + unsigned Count = countPopulation(Mask); if (isSGPRClass(RC)) { switch (Count) { case 1: |
