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author | Tom Stellard <tstellar@redhat.com> | 2018-06-22 03:04:35 +0000 |
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committer | Tom Stellard <tstellar@redhat.com> | 2018-06-22 03:04:35 +0000 |
commit | 6af73076505d9a845740c99b0fb89898dab36797 (patch) | |
tree | 38013a881f0e255954ef6ea37d8763a1f2da63cb /llvm/lib/Target/AMDGPU | |
parent | 26fac0f8e11c10caae3bbf731cfa3ad74fc9d826 (diff) | |
download | bcm5719-llvm-6af73076505d9a845740c99b0fb89898dab36797.tar.gz bcm5719-llvm-6af73076505d9a845740c99b0fb89898dab36797.zip |
AMDGPU/GlobalISel: Default to using TableGen'd instruction selector
Summary:
We can select all instructions that are marked as legal in a full piglit run,
so now is a good time to make the TableGen'd instruction selector default
for all opcodes. This is NFC for a full piglit run, which is why there are
no tests.
Reviewers: arsenm, nhaehnle
Subscribers: kzhuravl, wdng, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D48198
llvm-svn: 335319
Diffstat (limited to 'llvm/lib/Target/AMDGPU')
-rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp | 7 |
1 files changed, 0 insertions, 7 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp index 80a1bc9fe17..80f062b7daa 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp @@ -536,13 +536,6 @@ bool AMDGPUInstructionSelector::select(MachineInstr &I, switch (I.getOpcode()) { default: - break; - case TargetOpcode::G_ASHR: - case TargetOpcode::G_SITOFP: - case TargetOpcode::G_FMUL: - case TargetOpcode::G_FADD: - case TargetOpcode::G_FPTOUI: - case TargetOpcode::G_OR: return selectImpl(I, CoverageInfo); case TargetOpcode::G_ADD: return selectG_ADD(I); |