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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2015-08-26 20:48:04 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2015-08-26 20:48:04 +0000 |
| commit | 5e7f95e5671bd744d1d5f2f604f51fcfbeca99b5 (patch) | |
| tree | 8c8f8e8abfb88dbdac94d4df03f2eaf112a774c5 /llvm/lib/Target/AMDGPU | |
| parent | 445833cc91ea21f3fb79eb402034e6e6544dbbcf (diff) | |
| download | bcm5719-llvm-5e7f95e5671bd744d1d5f2f604f51fcfbeca99b5.tar.gz bcm5719-llvm-5e7f95e5671bd744d1d5f2f604f51fcfbeca99b5.zip | |
AMDGPU: Don't reprocess instructions when splitting i64 bcnt
llvm-svn: 246079
Diffstat (limited to 'llvm/lib/Target/AMDGPU')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp index 0bd0aba4954..d6f70a6da46 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp @@ -2513,18 +2513,19 @@ void SIInstrInfo::splitScalar64BitBCNT(SmallVectorImpl<MachineInstr *> &Worklist MachineOperand SrcRegSub1 = buildExtractSubRegOrImm(MII, MRI, Src, SrcRC, AMDGPU::sub1, SrcSubRC); - MachineInstr *First = BuildMI(MBB, MII, DL, InstDesc, MidReg) + BuildMI(MBB, MII, DL, InstDesc, MidReg) .addOperand(SrcRegSub0) .addImm(0); - MachineInstr *Second = BuildMI(MBB, MII, DL, InstDesc, ResultReg) + BuildMI(MBB, MII, DL, InstDesc, ResultReg) .addOperand(SrcRegSub1) .addReg(MidReg); MRI.replaceRegWith(Dest.getReg(), ResultReg); - Worklist.push_back(First); - Worklist.push_back(Second); + // We don't need to legalize operands here. src0 for etiher instruction can be + // an SGPR, and the second input is unused or determined here. + addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist); } void SIInstrInfo::splitScalar64BitBFE(SmallVectorImpl<MachineInstr *> &Worklist, |
