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| author | Joel Jones <joelkevinjones@gmail.com> | 2016-07-25 17:18:28 +0000 |
|---|---|---|
| committer | Joel Jones <joelkevinjones@gmail.com> | 2016-07-25 17:18:28 +0000 |
| commit | 373d7d30dd59a536f8d97745922db962bbdd1e59 (patch) | |
| tree | dae823a6f7e055e22818e6a54e6f2faa190a8027 /llvm/lib/Target/AMDGPU | |
| parent | fe58327146b212433f9d015c1f6d60d076ad8475 (diff) | |
| download | bcm5719-llvm-373d7d30dd59a536f8d97745922db962bbdd1e59.tar.gz bcm5719-llvm-373d7d30dd59a536f8d97745922db962bbdd1e59.zip | |
MC] Provide an MCTargetOptions to implementors of MCAsmBackendCtorTy, NFC
Some targets, notably AArch64 for ILP32, have different relocation encodings
based upon the ABI. This is an enabling change, so a future patch can use the
ABIName from MCTargetOptions to chose which relocations to use. Tested using
check-llvm.
The corresponding change to clang is in: http://reviews.llvm.org/D16538
Patch by: Joel Jones
Differential Revision: https://reviews.llvm.org/D16213
llvm-svn: 276654
Diffstat (limited to 'llvm/lib/Target/AMDGPU')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp | 3 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h | 4 |
2 files changed, 5 insertions, 2 deletions
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp index 1cb9d21408c..9d153f7f32b 100644 --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp @@ -171,7 +171,8 @@ public: MCAsmBackend *llvm::createAMDGPUAsmBackend(const Target &T, const MCRegisterInfo &MRI, - const Triple &TT, StringRef CPU) { + const Triple &TT, StringRef CPU, + const MCTargetOptions &Options) { // Use 64-bit ELF for amdgcn return new ELFAMDGPUAsmBackend(T, TT); } diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h index 9ab7940812b..5048c6d96bd 100644 --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h @@ -27,6 +27,7 @@ class MCInstrInfo; class MCObjectWriter; class MCRegisterInfo; class MCSubtargetInfo; +class MCTargetOptions; class Target; class Triple; class raw_pwrite_stream; @@ -44,7 +45,8 @@ MCCodeEmitter *createSIMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx); MCAsmBackend *createAMDGPUAsmBackend(const Target &T, const MCRegisterInfo &MRI, - const Triple &TT, StringRef CPU); + const Triple &TT, StringRef CPU, + const MCTargetOptions &Options); MCObjectWriter *createAMDGPUELFObjectWriter(bool Is64Bit, bool HasRelocationAddend, |
