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| author | Konstantin Zhuravlyov <kzhuravl_dev@outlook.com> | 2016-11-16 03:16:26 +0000 |
|---|---|---|
| committer | Konstantin Zhuravlyov <kzhuravl_dev@outlook.com> | 2016-11-16 03:16:26 +0000 |
| commit | 2a87a42035a1b7502b6359f31b24ade3a6ad36e3 (patch) | |
| tree | 826c01202f8c3b60edd5e5bc960229e70b603b7e /llvm/lib/Target/AMDGPU | |
| parent | 6eec7d4158fdb130b8f6473f7259211a8aa79f75 (diff) | |
| download | bcm5719-llvm-2a87a42035a1b7502b6359f31b24ade3a6ad36e3.tar.gz bcm5719-llvm-2a87a42035a1b7502b6359f31b24ade3a6ad36e3.zip | |
[AMDGPU] Handle f16 select{_cc}
- Select `select` to `v_cndmask_b32`
- Expand `select_cc`
- Refactor patterns
Differential Revision: https://reviews.llvm.org/D26714
llvm-svn: 287074
Diffstat (limited to 'llvm/lib/Target/AMDGPU')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 1 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIInstructions.td | 22 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/VOP3Instructions.td | 5 |
3 files changed, 13 insertions, 15 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index a0650d407ef..65898fc4b2a 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -289,6 +289,7 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM, setOperationAction(ISD::FSIN, MVT::f16, Promote); // F16 - VOP2 Actions. + setOperationAction(ISD::SELECT_CC, MVT::f16, Expand); setOperationAction(ISD::FMAXNUM, MVT::f16, Legal); setOperationAction(ISD::FMINNUM, MVT::f16, Legal); setOperationAction(ISD::FDIV, MVT::f16, Promote); diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td index 423599d8ccf..14e4b737315 100644 --- a/llvm/lib/Target/AMDGPU/SIInstructions.td +++ b/llvm/lib/Target/AMDGPU/SIInstructions.td @@ -468,16 +468,23 @@ def : Pat < // VOP2 Patterns //===----------------------------------------------------------------------===// +multiclass SelectPat<ValueType vt, Instruction inst> { + def : Pat < + (vt (select i1:$src0, vt:$src1, vt:$src2)), + (inst $src2, $src1, $src0) + >; +} + +defm : SelectPat<i16, V_CNDMASK_B32_e64>; +defm : SelectPat<i32, V_CNDMASK_B32_e64>; +defm : SelectPat<f16, V_CNDMASK_B32_e64>; +defm : SelectPat<f32, V_CNDMASK_B32_e64>; + def : Pat < (i32 (add (i32 (ctpop i32:$popcnt)), i32:$val)), (V_BCNT_U32_B32_e64 $popcnt, $val) >; -def : Pat < - (i32 (select i1:$src0, i32:$src1, i32:$src2)), - (V_CNDMASK_B32_e64 $src2, $src1, $src0) ->; - // Pattern for V_MAC_F16 def : Pat < (f16 (fmad (VOP3NoMods0 f16:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod), @@ -990,11 +997,6 @@ def : Pat < (V_ALIGNBIT_B32 $a, $a, (i32 8))) >; -def : Pat < - (f32 (select i1:$src2, f32:$src1, f32:$src0)), - (V_CNDMASK_B32_e64 $src0, $src1, $src2) ->; - multiclass BFMPatterns <ValueType vt, InstSI BFM, InstSI MOV> { def : Pat < (vt (shl (vt (add (vt (shl 1, vt:$a)), -1)), vt:$b)), diff --git a/llvm/lib/Target/AMDGPU/VOP3Instructions.td b/llvm/lib/Target/AMDGPU/VOP3Instructions.td index 4f8b680e52f..5efa64d25ce 100644 --- a/llvm/lib/Target/AMDGPU/VOP3Instructions.td +++ b/llvm/lib/Target/AMDGPU/VOP3Instructions.td @@ -232,11 +232,6 @@ def V_MAD_I16 : VOP3Inst <"v_mad_i16", VOP3_Profile<VOP_I16_I16_I16_I16>>; } // End SubtargetPredicate = isVI -def : Pat < - (i16 (select i1:$src0, i16:$src1, i16:$src2)), - (V_CNDMASK_B32_e64 $src2, $src1, $src0) ->; - let Predicates = [isVI] in { multiclass Tenary_i16_Pats <SDPatternOperator op1, SDPatternOperator op2, |
