diff options
| author | Artem Tamazov <artem.tamazov@amd.com> | 2017-02-03 12:47:30 +0000 |
|---|---|---|
| committer | Artem Tamazov <artem.tamazov@amd.com> | 2017-02-03 12:47:30 +0000 |
| commit | 43b61561b065a27dc96fd6ec1f6fa7691d2c82b1 (patch) | |
| tree | fd79a87ab4ff9dd71a012b6ef343be4a8e2038e7 /llvm/lib/Target/AMDGPU/Utils | |
| parent | a0d9f2582b7c31e604f4dc82fd5eae10d33aae7e (diff) | |
| download | bcm5719-llvm-43b61561b065a27dc96fd6ec1f6fa7691d2c82b1.tar.gz bcm5719-llvm-43b61561b065a27dc96fd6ec1f6fa7691d2c82b1.zip | |
[AMDGPU][mc] Fix AddressSanitizer leftover issue in gfx7_asm_all test
Issue occurs when assembling "ds_ordered_count v0, v0 gds".
llvm-svn: 294004
Diffstat (limited to 'llvm/lib/Target/AMDGPU/Utils')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp index 70ed40ec3b0..25e8f4b621c 100644 --- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp +++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp @@ -335,14 +335,14 @@ unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI) { } bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo) { - assert(OpNo <= Desc.NumOperands); + assert(OpNo < Desc.NumOperands); unsigned OpType = Desc.OpInfo[OpNo].OperandType; return OpType >= AMDGPU::OPERAND_SRC_FIRST && OpType <= AMDGPU::OPERAND_SRC_LAST; } bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo) { - assert(OpNo <= Desc.NumOperands); + assert(OpNo < Desc.NumOperands); unsigned OpType = Desc.OpInfo[OpNo].OperandType; switch (OpType) { case AMDGPU::OPERAND_REG_IMM_FP32: @@ -358,7 +358,7 @@ bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo) { } bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo) { - assert(OpNo <= Desc.NumOperands); + assert(OpNo < Desc.NumOperands); unsigned OpType = Desc.OpInfo[OpNo].OperandType; return OpType >= AMDGPU::OPERAND_REG_INLINE_C_FIRST && OpType <= AMDGPU::OPERAND_REG_INLINE_C_LAST; @@ -402,7 +402,7 @@ unsigned getRegBitWidth(const MCRegisterClass &RC) { unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc, unsigned OpNo) { - assert(OpNo <= Desc.NumOperands); + assert(OpNo < Desc.NumOperands); unsigned RCID = Desc.OpInfo[OpNo].RegClass; return getRegBitWidth(MRI->getRegClass(RCID)) / 8; } |
